1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2013 Ideas On Board SPRL 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A7790_H__ 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A7790_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* CPG */ 10*4882a593Smuzhiyun #define R8A7790_CLK_MAIN 0 11*4882a593Smuzhiyun #define R8A7790_CLK_PLL0 1 12*4882a593Smuzhiyun #define R8A7790_CLK_PLL1 2 13*4882a593Smuzhiyun #define R8A7790_CLK_PLL3 3 14*4882a593Smuzhiyun #define R8A7790_CLK_LB 4 15*4882a593Smuzhiyun #define R8A7790_CLK_QSPI 5 16*4882a593Smuzhiyun #define R8A7790_CLK_SDH 6 17*4882a593Smuzhiyun #define R8A7790_CLK_SD0 7 18*4882a593Smuzhiyun #define R8A7790_CLK_SD1 8 19*4882a593Smuzhiyun #define R8A7790_CLK_Z 9 20*4882a593Smuzhiyun #define R8A7790_CLK_RCAN 10 21*4882a593Smuzhiyun #define R8A7790_CLK_ADSP 11 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* MSTP0 */ 24*4882a593Smuzhiyun #define R8A7790_CLK_MSIOF0 0 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* MSTP1 */ 27*4882a593Smuzhiyun #define R8A7790_CLK_VCP1 0 28*4882a593Smuzhiyun #define R8A7790_CLK_VCP0 1 29*4882a593Smuzhiyun #define R8A7790_CLK_VPC1 2 30*4882a593Smuzhiyun #define R8A7790_CLK_VPC0 3 31*4882a593Smuzhiyun #define R8A7790_CLK_JPU 6 32*4882a593Smuzhiyun #define R8A7790_CLK_SSP1 9 33*4882a593Smuzhiyun #define R8A7790_CLK_TMU1 11 34*4882a593Smuzhiyun #define R8A7790_CLK_3DG 12 35*4882a593Smuzhiyun #define R8A7790_CLK_2DDMAC 15 36*4882a593Smuzhiyun #define R8A7790_CLK_FDP1_2 17 37*4882a593Smuzhiyun #define R8A7790_CLK_FDP1_1 18 38*4882a593Smuzhiyun #define R8A7790_CLK_FDP1_0 19 39*4882a593Smuzhiyun #define R8A7790_CLK_TMU3 21 40*4882a593Smuzhiyun #define R8A7790_CLK_TMU2 22 41*4882a593Smuzhiyun #define R8A7790_CLK_CMT0 24 42*4882a593Smuzhiyun #define R8A7790_CLK_TMU0 25 43*4882a593Smuzhiyun #define R8A7790_CLK_VSP1_DU1 27 44*4882a593Smuzhiyun #define R8A7790_CLK_VSP1_DU0 28 45*4882a593Smuzhiyun #define R8A7790_CLK_VSP1_R 30 46*4882a593Smuzhiyun #define R8A7790_CLK_VSP1_S 31 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* MSTP2 */ 49*4882a593Smuzhiyun #define R8A7790_CLK_SCIFA2 2 50*4882a593Smuzhiyun #define R8A7790_CLK_SCIFA1 3 51*4882a593Smuzhiyun #define R8A7790_CLK_SCIFA0 4 52*4882a593Smuzhiyun #define R8A7790_CLK_MSIOF2 5 53*4882a593Smuzhiyun #define R8A7790_CLK_SCIFB0 6 54*4882a593Smuzhiyun #define R8A7790_CLK_SCIFB1 7 55*4882a593Smuzhiyun #define R8A7790_CLK_MSIOF1 8 56*4882a593Smuzhiyun #define R8A7790_CLK_MSIOF3 15 57*4882a593Smuzhiyun #define R8A7790_CLK_SCIFB2 16 58*4882a593Smuzhiyun #define R8A7790_CLK_SYS_DMAC1 18 59*4882a593Smuzhiyun #define R8A7790_CLK_SYS_DMAC0 19 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* MSTP3 */ 62*4882a593Smuzhiyun #define R8A7790_CLK_IIC2 0 63*4882a593Smuzhiyun #define R8A7790_CLK_TPU0 4 64*4882a593Smuzhiyun #define R8A7790_CLK_MMCIF1 5 65*4882a593Smuzhiyun #define R8A7790_CLK_SCIF2 10 66*4882a593Smuzhiyun #define R8A7790_CLK_SDHI3 11 67*4882a593Smuzhiyun #define R8A7790_CLK_SDHI2 12 68*4882a593Smuzhiyun #define R8A7790_CLK_SDHI1 13 69*4882a593Smuzhiyun #define R8A7790_CLK_SDHI0 14 70*4882a593Smuzhiyun #define R8A7790_CLK_MMCIF0 15 71*4882a593Smuzhiyun #define R8A7790_CLK_IIC0 18 72*4882a593Smuzhiyun #define R8A7790_CLK_PCIEC 19 73*4882a593Smuzhiyun #define R8A7790_CLK_IIC1 23 74*4882a593Smuzhiyun #define R8A7790_CLK_SSUSB 28 75*4882a593Smuzhiyun #define R8A7790_CLK_CMT1 29 76*4882a593Smuzhiyun #define R8A7790_CLK_USBDMAC0 30 77*4882a593Smuzhiyun #define R8A7790_CLK_USBDMAC1 31 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* MSTP4 */ 80*4882a593Smuzhiyun #define R8A7790_CLK_IRQC 7 81*4882a593Smuzhiyun #define R8A7790_CLK_INTC_SYS 8 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* MSTP5 */ 84*4882a593Smuzhiyun #define R8A7790_CLK_AUDIO_DMAC1 1 85*4882a593Smuzhiyun #define R8A7790_CLK_AUDIO_DMAC0 2 86*4882a593Smuzhiyun #define R8A7790_CLK_ADSP_MOD 6 87*4882a593Smuzhiyun #define R8A7790_CLK_THERMAL 22 88*4882a593Smuzhiyun #define R8A7790_CLK_PWM 23 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* MSTP7 */ 91*4882a593Smuzhiyun #define R8A7790_CLK_EHCI 3 92*4882a593Smuzhiyun #define R8A7790_CLK_HSUSB 4 93*4882a593Smuzhiyun #define R8A7790_CLK_HSCIF1 16 94*4882a593Smuzhiyun #define R8A7790_CLK_HSCIF0 17 95*4882a593Smuzhiyun #define R8A7790_CLK_SCIF1 20 96*4882a593Smuzhiyun #define R8A7790_CLK_SCIF0 21 97*4882a593Smuzhiyun #define R8A7790_CLK_DU2 22 98*4882a593Smuzhiyun #define R8A7790_CLK_DU1 23 99*4882a593Smuzhiyun #define R8A7790_CLK_DU0 24 100*4882a593Smuzhiyun #define R8A7790_CLK_LVDS1 25 101*4882a593Smuzhiyun #define R8A7790_CLK_LVDS0 26 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* MSTP8 */ 104*4882a593Smuzhiyun #define R8A7790_CLK_MLB 2 105*4882a593Smuzhiyun #define R8A7790_CLK_VIN3 8 106*4882a593Smuzhiyun #define R8A7790_CLK_VIN2 9 107*4882a593Smuzhiyun #define R8A7790_CLK_VIN1 10 108*4882a593Smuzhiyun #define R8A7790_CLK_VIN0 11 109*4882a593Smuzhiyun #define R8A7790_CLK_ETHERAVB 12 110*4882a593Smuzhiyun #define R8A7790_CLK_ETHER 13 111*4882a593Smuzhiyun #define R8A7790_CLK_SATA1 14 112*4882a593Smuzhiyun #define R8A7790_CLK_SATA0 15 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* MSTP9 */ 115*4882a593Smuzhiyun #define R8A7790_CLK_GPIO5 7 116*4882a593Smuzhiyun #define R8A7790_CLK_GPIO4 8 117*4882a593Smuzhiyun #define R8A7790_CLK_GPIO3 9 118*4882a593Smuzhiyun #define R8A7790_CLK_GPIO2 10 119*4882a593Smuzhiyun #define R8A7790_CLK_GPIO1 11 120*4882a593Smuzhiyun #define R8A7790_CLK_GPIO0 12 121*4882a593Smuzhiyun #define R8A7790_CLK_RCAN1 15 122*4882a593Smuzhiyun #define R8A7790_CLK_RCAN0 16 123*4882a593Smuzhiyun #define R8A7790_CLK_QSPI_MOD 17 124*4882a593Smuzhiyun #define R8A7790_CLK_IICDVFS 26 125*4882a593Smuzhiyun #define R8A7790_CLK_I2C3 28 126*4882a593Smuzhiyun #define R8A7790_CLK_I2C2 29 127*4882a593Smuzhiyun #define R8A7790_CLK_I2C1 30 128*4882a593Smuzhiyun #define R8A7790_CLK_I2C0 31 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* MSTP10 */ 131*4882a593Smuzhiyun #define R8A7790_CLK_SSI_ALL 5 132*4882a593Smuzhiyun #define R8A7790_CLK_SSI9 6 133*4882a593Smuzhiyun #define R8A7790_CLK_SSI8 7 134*4882a593Smuzhiyun #define R8A7790_CLK_SSI7 8 135*4882a593Smuzhiyun #define R8A7790_CLK_SSI6 9 136*4882a593Smuzhiyun #define R8A7790_CLK_SSI5 10 137*4882a593Smuzhiyun #define R8A7790_CLK_SSI4 11 138*4882a593Smuzhiyun #define R8A7790_CLK_SSI3 12 139*4882a593Smuzhiyun #define R8A7790_CLK_SSI2 13 140*4882a593Smuzhiyun #define R8A7790_CLK_SSI1 14 141*4882a593Smuzhiyun #define R8A7790_CLK_SSI0 15 142*4882a593Smuzhiyun #define R8A7790_CLK_SCU_ALL 17 143*4882a593Smuzhiyun #define R8A7790_CLK_SCU_DVC1 18 144*4882a593Smuzhiyun #define R8A7790_CLK_SCU_DVC0 19 145*4882a593Smuzhiyun #define R8A7790_CLK_SCU_CTU1_MIX1 20 146*4882a593Smuzhiyun #define R8A7790_CLK_SCU_CTU0_MIX0 21 147*4882a593Smuzhiyun #define R8A7790_CLK_SCU_SRC9 22 148*4882a593Smuzhiyun #define R8A7790_CLK_SCU_SRC8 23 149*4882a593Smuzhiyun #define R8A7790_CLK_SCU_SRC7 24 150*4882a593Smuzhiyun #define R8A7790_CLK_SCU_SRC6 25 151*4882a593Smuzhiyun #define R8A7790_CLK_SCU_SRC5 26 152*4882a593Smuzhiyun #define R8A7790_CLK_SCU_SRC4 27 153*4882a593Smuzhiyun #define R8A7790_CLK_SCU_SRC3 28 154*4882a593Smuzhiyun #define R8A7790_CLK_SCU_SRC2 29 155*4882a593Smuzhiyun #define R8A7790_CLK_SCU_SRC1 30 156*4882a593Smuzhiyun #define R8A7790_CLK_SCU_SRC0 31 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */ 159