1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2013 Horms Solutions Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Contact: Simon Horman <horms@verge.net.au> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A7779_H__ 9*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A7779_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* CPG */ 12*4882a593Smuzhiyun #define R8A7779_CLK_PLLA 0 13*4882a593Smuzhiyun #define R8A7779_CLK_Z 1 14*4882a593Smuzhiyun #define R8A7779_CLK_ZS 2 15*4882a593Smuzhiyun #define R8A7779_CLK_S 3 16*4882a593Smuzhiyun #define R8A7779_CLK_S1 4 17*4882a593Smuzhiyun #define R8A7779_CLK_P 5 18*4882a593Smuzhiyun #define R8A7779_CLK_B 6 19*4882a593Smuzhiyun #define R8A7779_CLK_OUT 7 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* MSTP 0 */ 22*4882a593Smuzhiyun #define R8A7779_CLK_HSPI 7 23*4882a593Smuzhiyun #define R8A7779_CLK_TMU2 14 24*4882a593Smuzhiyun #define R8A7779_CLK_TMU1 15 25*4882a593Smuzhiyun #define R8A7779_CLK_TMU0 16 26*4882a593Smuzhiyun #define R8A7779_CLK_HSCIF1 18 27*4882a593Smuzhiyun #define R8A7779_CLK_HSCIF0 19 28*4882a593Smuzhiyun #define R8A7779_CLK_SCIF5 21 29*4882a593Smuzhiyun #define R8A7779_CLK_SCIF4 22 30*4882a593Smuzhiyun #define R8A7779_CLK_SCIF3 23 31*4882a593Smuzhiyun #define R8A7779_CLK_SCIF2 24 32*4882a593Smuzhiyun #define R8A7779_CLK_SCIF1 25 33*4882a593Smuzhiyun #define R8A7779_CLK_SCIF0 26 34*4882a593Smuzhiyun #define R8A7779_CLK_I2C3 27 35*4882a593Smuzhiyun #define R8A7779_CLK_I2C2 28 36*4882a593Smuzhiyun #define R8A7779_CLK_I2C1 29 37*4882a593Smuzhiyun #define R8A7779_CLK_I2C0 30 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* MSTP 1 */ 40*4882a593Smuzhiyun #define R8A7779_CLK_USB01 0 41*4882a593Smuzhiyun #define R8A7779_CLK_USB2 1 42*4882a593Smuzhiyun #define R8A7779_CLK_DU 3 43*4882a593Smuzhiyun #define R8A7779_CLK_VIN2 8 44*4882a593Smuzhiyun #define R8A7779_CLK_VIN1 9 45*4882a593Smuzhiyun #define R8A7779_CLK_VIN0 10 46*4882a593Smuzhiyun #define R8A7779_CLK_ETHER 14 47*4882a593Smuzhiyun #define R8A7779_CLK_SATA 15 48*4882a593Smuzhiyun #define R8A7779_CLK_PCIE 16 49*4882a593Smuzhiyun #define R8A7779_CLK_VIN3 20 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* MSTP 3 */ 52*4882a593Smuzhiyun #define R8A7779_CLK_SDHI3 20 53*4882a593Smuzhiyun #define R8A7779_CLK_SDHI2 21 54*4882a593Smuzhiyun #define R8A7779_CLK_SDHI1 22 55*4882a593Smuzhiyun #define R8A7779_CLK_SDHI0 23 56*4882a593Smuzhiyun #define R8A7779_CLK_MMC1 30 57*4882a593Smuzhiyun #define R8A7779_CLK_MMC0 31 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */ 61