1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2014 Ulrich Hecht 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A7778_H__ 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A7778_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* CPG */ 10*4882a593Smuzhiyun #define R8A7778_CLK_PLLA 0 11*4882a593Smuzhiyun #define R8A7778_CLK_PLLB 1 12*4882a593Smuzhiyun #define R8A7778_CLK_B 2 13*4882a593Smuzhiyun #define R8A7778_CLK_OUT 3 14*4882a593Smuzhiyun #define R8A7778_CLK_P 4 15*4882a593Smuzhiyun #define R8A7778_CLK_S 5 16*4882a593Smuzhiyun #define R8A7778_CLK_S1 6 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* MSTP0 */ 19*4882a593Smuzhiyun #define R8A7778_CLK_I2C0 30 20*4882a593Smuzhiyun #define R8A7778_CLK_I2C1 29 21*4882a593Smuzhiyun #define R8A7778_CLK_I2C2 28 22*4882a593Smuzhiyun #define R8A7778_CLK_I2C3 27 23*4882a593Smuzhiyun #define R8A7778_CLK_SCIF0 26 24*4882a593Smuzhiyun #define R8A7778_CLK_SCIF1 25 25*4882a593Smuzhiyun #define R8A7778_CLK_SCIF2 24 26*4882a593Smuzhiyun #define R8A7778_CLK_SCIF3 23 27*4882a593Smuzhiyun #define R8A7778_CLK_SCIF4 22 28*4882a593Smuzhiyun #define R8A7778_CLK_SCIF5 21 29*4882a593Smuzhiyun #define R8A7778_CLK_HSCIF0 19 30*4882a593Smuzhiyun #define R8A7778_CLK_HSCIF1 18 31*4882a593Smuzhiyun #define R8A7778_CLK_TMU0 16 32*4882a593Smuzhiyun #define R8A7778_CLK_TMU1 15 33*4882a593Smuzhiyun #define R8A7778_CLK_TMU2 14 34*4882a593Smuzhiyun #define R8A7778_CLK_SSI0 12 35*4882a593Smuzhiyun #define R8A7778_CLK_SSI1 11 36*4882a593Smuzhiyun #define R8A7778_CLK_SSI2 10 37*4882a593Smuzhiyun #define R8A7778_CLK_SSI3 9 38*4882a593Smuzhiyun #define R8A7778_CLK_SRU 8 39*4882a593Smuzhiyun #define R8A7778_CLK_HSPI 7 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* MSTP1 */ 42*4882a593Smuzhiyun #define R8A7778_CLK_ETHER 14 43*4882a593Smuzhiyun #define R8A7778_CLK_VIN0 10 44*4882a593Smuzhiyun #define R8A7778_CLK_VIN1 9 45*4882a593Smuzhiyun #define R8A7778_CLK_USB 0 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* MSTP3 */ 48*4882a593Smuzhiyun #define R8A7778_CLK_MMC 31 49*4882a593Smuzhiyun #define R8A7778_CLK_SDHI0 23 50*4882a593Smuzhiyun #define R8A7778_CLK_SDHI1 22 51*4882a593Smuzhiyun #define R8A7778_CLK_SDHI2 21 52*4882a593Smuzhiyun #define R8A7778_CLK_SSI4 11 53*4882a593Smuzhiyun #define R8A7778_CLK_SSI5 10 54*4882a593Smuzhiyun #define R8A7778_CLK_SSI6 9 55*4882a593Smuzhiyun #define R8A7778_CLK_SSI7 8 56*4882a593Smuzhiyun #define R8A7778_CLK_SSI8 7 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* MSTP5 */ 59*4882a593Smuzhiyun #define R8A7778_CLK_SRU_SRC0 31 60*4882a593Smuzhiyun #define R8A7778_CLK_SRU_SRC1 30 61*4882a593Smuzhiyun #define R8A7778_CLK_SRU_SRC2 29 62*4882a593Smuzhiyun #define R8A7778_CLK_SRU_SRC3 28 63*4882a593Smuzhiyun #define R8A7778_CLK_SRU_SRC4 27 64*4882a593Smuzhiyun #define R8A7778_CLK_SRU_SRC5 26 65*4882a593Smuzhiyun #define R8A7778_CLK_SRU_SRC6 25 66*4882a593Smuzhiyun #define R8A7778_CLK_SRU_SRC7 24 67*4882a593Smuzhiyun #define R8A7778_CLK_SRU_SRC8 23 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A7778_H__ */ 70