1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (C) 2020 Renesas Electronics Corp. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ 6*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* R8A774E1 CPG Core Clocks */ 11*4882a593Smuzhiyun #define R8A774E1_CLK_Z 0 12*4882a593Smuzhiyun #define R8A774E1_CLK_Z2 1 13*4882a593Smuzhiyun #define R8A774E1_CLK_ZG 2 14*4882a593Smuzhiyun #define R8A774E1_CLK_ZTR 3 15*4882a593Smuzhiyun #define R8A774E1_CLK_ZTRD2 4 16*4882a593Smuzhiyun #define R8A774E1_CLK_ZT 5 17*4882a593Smuzhiyun #define R8A774E1_CLK_ZX 6 18*4882a593Smuzhiyun #define R8A774E1_CLK_S0D1 7 19*4882a593Smuzhiyun #define R8A774E1_CLK_S0D2 8 20*4882a593Smuzhiyun #define R8A774E1_CLK_S0D3 9 21*4882a593Smuzhiyun #define R8A774E1_CLK_S0D4 10 22*4882a593Smuzhiyun #define R8A774E1_CLK_S0D6 11 23*4882a593Smuzhiyun #define R8A774E1_CLK_S0D8 12 24*4882a593Smuzhiyun #define R8A774E1_CLK_S0D12 13 25*4882a593Smuzhiyun #define R8A774E1_CLK_S1D2 14 26*4882a593Smuzhiyun #define R8A774E1_CLK_S1D4 15 27*4882a593Smuzhiyun #define R8A774E1_CLK_S2D1 16 28*4882a593Smuzhiyun #define R8A774E1_CLK_S2D2 17 29*4882a593Smuzhiyun #define R8A774E1_CLK_S2D4 18 30*4882a593Smuzhiyun #define R8A774E1_CLK_S3D1 19 31*4882a593Smuzhiyun #define R8A774E1_CLK_S3D2 20 32*4882a593Smuzhiyun #define R8A774E1_CLK_S3D4 21 33*4882a593Smuzhiyun #define R8A774E1_CLK_LB 22 34*4882a593Smuzhiyun #define R8A774E1_CLK_CL 23 35*4882a593Smuzhiyun #define R8A774E1_CLK_ZB3 24 36*4882a593Smuzhiyun #define R8A774E1_CLK_ZB3D2 25 37*4882a593Smuzhiyun #define R8A774E1_CLK_ZB3D4 26 38*4882a593Smuzhiyun #define R8A774E1_CLK_CR 27 39*4882a593Smuzhiyun #define R8A774E1_CLK_CRD2 28 40*4882a593Smuzhiyun #define R8A774E1_CLK_SD0H 29 41*4882a593Smuzhiyun #define R8A774E1_CLK_SD0 30 42*4882a593Smuzhiyun #define R8A774E1_CLK_SD1H 31 43*4882a593Smuzhiyun #define R8A774E1_CLK_SD1 32 44*4882a593Smuzhiyun #define R8A774E1_CLK_SD2H 33 45*4882a593Smuzhiyun #define R8A774E1_CLK_SD2 34 46*4882a593Smuzhiyun #define R8A774E1_CLK_SD3H 35 47*4882a593Smuzhiyun #define R8A774E1_CLK_SD3 36 48*4882a593Smuzhiyun #define R8A774E1_CLK_RPC 37 49*4882a593Smuzhiyun #define R8A774E1_CLK_RPCD2 38 50*4882a593Smuzhiyun #define R8A774E1_CLK_MSO 39 51*4882a593Smuzhiyun #define R8A774E1_CLK_HDMI 40 52*4882a593Smuzhiyun #define R8A774E1_CLK_CSI0 41 53*4882a593Smuzhiyun #define R8A774E1_CLK_CP 42 54*4882a593Smuzhiyun #define R8A774E1_CLK_CPEX 43 55*4882a593Smuzhiyun #define R8A774E1_CLK_R 44 56*4882a593Smuzhiyun #define R8A774E1_CLK_OSC 45 57*4882a593Smuzhiyun #define R8A774E1_CLK_CANFD 46 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */ 60