1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (C) 2018 Renesas Electronics Corp. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ 6*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* r8a77470 CPG Core Clocks */ 11*4882a593Smuzhiyun #define R8A77470_CLK_Z2 0 12*4882a593Smuzhiyun #define R8A77470_CLK_ZTR 1 13*4882a593Smuzhiyun #define R8A77470_CLK_ZTRD2 2 14*4882a593Smuzhiyun #define R8A77470_CLK_ZT 3 15*4882a593Smuzhiyun #define R8A77470_CLK_ZX 4 16*4882a593Smuzhiyun #define R8A77470_CLK_ZS 5 17*4882a593Smuzhiyun #define R8A77470_CLK_HP 6 18*4882a593Smuzhiyun #define R8A77470_CLK_B 7 19*4882a593Smuzhiyun #define R8A77470_CLK_LB 8 20*4882a593Smuzhiyun #define R8A77470_CLK_P 9 21*4882a593Smuzhiyun #define R8A77470_CLK_CL 10 22*4882a593Smuzhiyun #define R8A77470_CLK_CP 11 23*4882a593Smuzhiyun #define R8A77470_CLK_M2 12 24*4882a593Smuzhiyun #define R8A77470_CLK_ZB3 13 25*4882a593Smuzhiyun #define R8A77470_CLK_SDH 14 26*4882a593Smuzhiyun #define R8A77470_CLK_SD0 15 27*4882a593Smuzhiyun #define R8A77470_CLK_SD1 16 28*4882a593Smuzhiyun #define R8A77470_CLK_SD2 17 29*4882a593Smuzhiyun #define R8A77470_CLK_MP 18 30*4882a593Smuzhiyun #define R8A77470_CLK_QSPI 19 31*4882a593Smuzhiyun #define R8A77470_CLK_CPEX 20 32*4882a593Smuzhiyun #define R8A77470_CLK_RCAN 21 33*4882a593Smuzhiyun #define R8A77470_CLK_R 22 34*4882a593Smuzhiyun #define R8A77470_CLK_OSC 23 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */ 37