1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (C) 2016 Cogent Embedded Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ 6*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* r8a7745 CPG Core Clocks */ 11*4882a593Smuzhiyun #define R8A7745_CLK_Z2 0 12*4882a593Smuzhiyun #define R8A7745_CLK_ZG 1 13*4882a593Smuzhiyun #define R8A7745_CLK_ZTR 2 14*4882a593Smuzhiyun #define R8A7745_CLK_ZTRD2 3 15*4882a593Smuzhiyun #define R8A7745_CLK_ZT 4 16*4882a593Smuzhiyun #define R8A7745_CLK_ZX 5 17*4882a593Smuzhiyun #define R8A7745_CLK_ZS 6 18*4882a593Smuzhiyun #define R8A7745_CLK_HP 7 19*4882a593Smuzhiyun #define R8A7745_CLK_B 9 20*4882a593Smuzhiyun #define R8A7745_CLK_LB 10 21*4882a593Smuzhiyun #define R8A7745_CLK_P 11 22*4882a593Smuzhiyun #define R8A7745_CLK_CL 12 23*4882a593Smuzhiyun #define R8A7745_CLK_CP 13 24*4882a593Smuzhiyun #define R8A7745_CLK_M2 14 25*4882a593Smuzhiyun #define R8A7745_CLK_ZB3 16 26*4882a593Smuzhiyun #define R8A7745_CLK_ZB3D2 17 27*4882a593Smuzhiyun #define R8A7745_CLK_DDR 18 28*4882a593Smuzhiyun #define R8A7745_CLK_SDH 19 29*4882a593Smuzhiyun #define R8A7745_CLK_SD0 20 30*4882a593Smuzhiyun #define R8A7745_CLK_SD2 21 31*4882a593Smuzhiyun #define R8A7745_CLK_SD3 22 32*4882a593Smuzhiyun #define R8A7745_CLK_MMC0 23 33*4882a593Smuzhiyun #define R8A7745_CLK_MP 24 34*4882a593Smuzhiyun #define R8A7745_CLK_QSPI 25 35*4882a593Smuzhiyun #define R8A7745_CLK_CPEX 26 36*4882a593Smuzhiyun #define R8A7745_CLK_RCAN 27 37*4882a593Smuzhiyun #define R8A7745_CLK_R 28 38*4882a593Smuzhiyun #define R8A7745_CLK_OSC 29 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ */ 41