1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (C) 2020 Renesas Electronics Corp. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ 6*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* r8a7742 CPG Core Clocks */ 11*4882a593Smuzhiyun #define R8A7742_CLK_Z 0 12*4882a593Smuzhiyun #define R8A7742_CLK_Z2 1 13*4882a593Smuzhiyun #define R8A7742_CLK_ZG 2 14*4882a593Smuzhiyun #define R8A7742_CLK_ZTR 3 15*4882a593Smuzhiyun #define R8A7742_CLK_ZTRD2 4 16*4882a593Smuzhiyun #define R8A7742_CLK_ZT 5 17*4882a593Smuzhiyun #define R8A7742_CLK_ZX 6 18*4882a593Smuzhiyun #define R8A7742_CLK_ZS 7 19*4882a593Smuzhiyun #define R8A7742_CLK_HP 8 20*4882a593Smuzhiyun #define R8A7742_CLK_B 9 21*4882a593Smuzhiyun #define R8A7742_CLK_LB 10 22*4882a593Smuzhiyun #define R8A7742_CLK_P 11 23*4882a593Smuzhiyun #define R8A7742_CLK_CL 12 24*4882a593Smuzhiyun #define R8A7742_CLK_M2 13 25*4882a593Smuzhiyun #define R8A7742_CLK_ZB3 14 26*4882a593Smuzhiyun #define R8A7742_CLK_ZB3D2 15 27*4882a593Smuzhiyun #define R8A7742_CLK_DDR 16 28*4882a593Smuzhiyun #define R8A7742_CLK_SDH 17 29*4882a593Smuzhiyun #define R8A7742_CLK_SD0 18 30*4882a593Smuzhiyun #define R8A7742_CLK_SD1 19 31*4882a593Smuzhiyun #define R8A7742_CLK_SD2 20 32*4882a593Smuzhiyun #define R8A7742_CLK_SD3 21 33*4882a593Smuzhiyun #define R8A7742_CLK_MMC0 22 34*4882a593Smuzhiyun #define R8A7742_CLK_MMC1 23 35*4882a593Smuzhiyun #define R8A7742_CLK_MP 24 36*4882a593Smuzhiyun #define R8A7742_CLK_QSPI 25 37*4882a593Smuzhiyun #define R8A7742_CLK_CP 26 38*4882a593Smuzhiyun #define R8A7742_CLK_RCAN 27 39*4882a593Smuzhiyun #define R8A7742_CLK_R 28 40*4882a593Smuzhiyun #define R8A7742_CLK_OSC 29 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */ 43