1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2014 Ulrich Hecht 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A7740_H__ 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A7740_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* CPG */ 10*4882a593Smuzhiyun #define R8A7740_CLK_SYSTEM 0 11*4882a593Smuzhiyun #define R8A7740_CLK_PLLC0 1 12*4882a593Smuzhiyun #define R8A7740_CLK_PLLC1 2 13*4882a593Smuzhiyun #define R8A7740_CLK_PLLC2 3 14*4882a593Smuzhiyun #define R8A7740_CLK_R 4 15*4882a593Smuzhiyun #define R8A7740_CLK_USB24S 5 16*4882a593Smuzhiyun #define R8A7740_CLK_I 6 17*4882a593Smuzhiyun #define R8A7740_CLK_ZG 7 18*4882a593Smuzhiyun #define R8A7740_CLK_B 8 19*4882a593Smuzhiyun #define R8A7740_CLK_M1 9 20*4882a593Smuzhiyun #define R8A7740_CLK_HP 10 21*4882a593Smuzhiyun #define R8A7740_CLK_HPP 11 22*4882a593Smuzhiyun #define R8A7740_CLK_USBP 12 23*4882a593Smuzhiyun #define R8A7740_CLK_S 13 24*4882a593Smuzhiyun #define R8A7740_CLK_ZB 14 25*4882a593Smuzhiyun #define R8A7740_CLK_M3 15 26*4882a593Smuzhiyun #define R8A7740_CLK_CP 16 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* MSTP1 */ 29*4882a593Smuzhiyun #define R8A7740_CLK_CEU21 28 30*4882a593Smuzhiyun #define R8A7740_CLK_CEU20 27 31*4882a593Smuzhiyun #define R8A7740_CLK_TMU0 25 32*4882a593Smuzhiyun #define R8A7740_CLK_LCDC1 17 33*4882a593Smuzhiyun #define R8A7740_CLK_IIC0 16 34*4882a593Smuzhiyun #define R8A7740_CLK_TMU1 11 35*4882a593Smuzhiyun #define R8A7740_CLK_LCDC0 0 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* MSTP2 */ 38*4882a593Smuzhiyun #define R8A7740_CLK_SCIFA6 30 39*4882a593Smuzhiyun #define R8A7740_CLK_INTCA 29 40*4882a593Smuzhiyun #define R8A7740_CLK_SCIFA7 22 41*4882a593Smuzhiyun #define R8A7740_CLK_DMAC1 18 42*4882a593Smuzhiyun #define R8A7740_CLK_DMAC2 17 43*4882a593Smuzhiyun #define R8A7740_CLK_DMAC3 16 44*4882a593Smuzhiyun #define R8A7740_CLK_USBDMAC 14 45*4882a593Smuzhiyun #define R8A7740_CLK_SCIFA5 7 46*4882a593Smuzhiyun #define R8A7740_CLK_SCIFB 6 47*4882a593Smuzhiyun #define R8A7740_CLK_SCIFA0 4 48*4882a593Smuzhiyun #define R8A7740_CLK_SCIFA1 3 49*4882a593Smuzhiyun #define R8A7740_CLK_SCIFA2 2 50*4882a593Smuzhiyun #define R8A7740_CLK_SCIFA3 1 51*4882a593Smuzhiyun #define R8A7740_CLK_SCIFA4 0 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* MSTP3 */ 54*4882a593Smuzhiyun #define R8A7740_CLK_CMT1 29 55*4882a593Smuzhiyun #define R8A7740_CLK_FSI 28 56*4882a593Smuzhiyun #define R8A7740_CLK_IIC1 23 57*4882a593Smuzhiyun #define R8A7740_CLK_USBF 20 58*4882a593Smuzhiyun #define R8A7740_CLK_SDHI0 14 59*4882a593Smuzhiyun #define R8A7740_CLK_SDHI1 13 60*4882a593Smuzhiyun #define R8A7740_CLK_MMC 12 61*4882a593Smuzhiyun #define R8A7740_CLK_GETHER 9 62*4882a593Smuzhiyun #define R8A7740_CLK_TPU0 4 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* MSTP4 */ 65*4882a593Smuzhiyun #define R8A7740_CLK_USBH 16 66*4882a593Smuzhiyun #define R8A7740_CLK_SDHI2 15 67*4882a593Smuzhiyun #define R8A7740_CLK_USBFUNC 7 68*4882a593Smuzhiyun #define R8A7740_CLK_USBPHY 6 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* SUBCK* */ 71*4882a593Smuzhiyun #define R8A7740_CLK_SUBCK 9 72*4882a593Smuzhiyun #define R8A7740_CLK_SUBCK2 10 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A7740_H__ */ 75