1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2014 Ulrich Hecht 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R8A73A4_H__ 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R8A73A4_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* CPG */ 10*4882a593Smuzhiyun #define R8A73A4_CLK_MAIN 0 11*4882a593Smuzhiyun #define R8A73A4_CLK_PLL0 1 12*4882a593Smuzhiyun #define R8A73A4_CLK_PLL1 2 13*4882a593Smuzhiyun #define R8A73A4_CLK_PLL2 3 14*4882a593Smuzhiyun #define R8A73A4_CLK_PLL2S 4 15*4882a593Smuzhiyun #define R8A73A4_CLK_PLL2H 5 16*4882a593Smuzhiyun #define R8A73A4_CLK_Z 6 17*4882a593Smuzhiyun #define R8A73A4_CLK_Z2 7 18*4882a593Smuzhiyun #define R8A73A4_CLK_I 8 19*4882a593Smuzhiyun #define R8A73A4_CLK_M3 9 20*4882a593Smuzhiyun #define R8A73A4_CLK_B 10 21*4882a593Smuzhiyun #define R8A73A4_CLK_M1 11 22*4882a593Smuzhiyun #define R8A73A4_CLK_M2 12 23*4882a593Smuzhiyun #define R8A73A4_CLK_ZX 13 24*4882a593Smuzhiyun #define R8A73A4_CLK_ZS 14 25*4882a593Smuzhiyun #define R8A73A4_CLK_HP 15 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* MSTP2 */ 28*4882a593Smuzhiyun #define R8A73A4_CLK_DMAC 18 29*4882a593Smuzhiyun #define R8A73A4_CLK_SCIFB3 17 30*4882a593Smuzhiyun #define R8A73A4_CLK_SCIFB2 16 31*4882a593Smuzhiyun #define R8A73A4_CLK_SCIFB1 7 32*4882a593Smuzhiyun #define R8A73A4_CLK_SCIFB0 6 33*4882a593Smuzhiyun #define R8A73A4_CLK_SCIFA0 4 34*4882a593Smuzhiyun #define R8A73A4_CLK_SCIFA1 3 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* MSTP3 */ 37*4882a593Smuzhiyun #define R8A73A4_CLK_CMT1 29 38*4882a593Smuzhiyun #define R8A73A4_CLK_IIC1 23 39*4882a593Smuzhiyun #define R8A73A4_CLK_IIC0 18 40*4882a593Smuzhiyun #define R8A73A4_CLK_IIC7 17 41*4882a593Smuzhiyun #define R8A73A4_CLK_IIC6 16 42*4882a593Smuzhiyun #define R8A73A4_CLK_MMCIF0 15 43*4882a593Smuzhiyun #define R8A73A4_CLK_SDHI0 14 44*4882a593Smuzhiyun #define R8A73A4_CLK_SDHI1 13 45*4882a593Smuzhiyun #define R8A73A4_CLK_SDHI2 12 46*4882a593Smuzhiyun #define R8A73A4_CLK_MMCIF1 5 47*4882a593Smuzhiyun #define R8A73A4_CLK_IIC2 0 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* MSTP4 */ 50*4882a593Smuzhiyun #define R8A73A4_CLK_IIC3 11 51*4882a593Smuzhiyun #define R8A73A4_CLK_IIC4 10 52*4882a593Smuzhiyun #define R8A73A4_CLK_IIC5 9 53*4882a593Smuzhiyun #define R8A73A4_CLK_INTC_SYS 8 54*4882a593Smuzhiyun #define R8A73A4_CLK_IRQC 7 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* MSTP5 */ 57*4882a593Smuzhiyun #define R8A73A4_CLK_THERMAL 22 58*4882a593Smuzhiyun #define R8A73A4_CLK_IIC8 15 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R8A73A4_H__ */ 61