1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (C) 2014 Renesas Solutions Corp. 4*4882a593Smuzhiyun * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_R7S72100_H__ 8*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_R7S72100_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define R7S72100_CLK_PLL 0 11*4882a593Smuzhiyun #define R7S72100_CLK_I 1 12*4882a593Smuzhiyun #define R7S72100_CLK_G 2 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* MSTP2 */ 15*4882a593Smuzhiyun #define R7S72100_CLK_CORESIGHT 0 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* MSTP3 */ 18*4882a593Smuzhiyun #define R7S72100_CLK_IEBUS 7 19*4882a593Smuzhiyun #define R7S72100_CLK_IRDA 6 20*4882a593Smuzhiyun #define R7S72100_CLK_LIN0 5 21*4882a593Smuzhiyun #define R7S72100_CLK_LIN1 4 22*4882a593Smuzhiyun #define R7S72100_CLK_MTU2 3 23*4882a593Smuzhiyun #define R7S72100_CLK_CAN 2 24*4882a593Smuzhiyun #define R7S72100_CLK_ADCPWR 1 25*4882a593Smuzhiyun #define R7S72100_CLK_PWM 0 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* MSTP4 */ 28*4882a593Smuzhiyun #define R7S72100_CLK_SCIF0 7 29*4882a593Smuzhiyun #define R7S72100_CLK_SCIF1 6 30*4882a593Smuzhiyun #define R7S72100_CLK_SCIF2 5 31*4882a593Smuzhiyun #define R7S72100_CLK_SCIF3 4 32*4882a593Smuzhiyun #define R7S72100_CLK_SCIF4 3 33*4882a593Smuzhiyun #define R7S72100_CLK_SCIF5 2 34*4882a593Smuzhiyun #define R7S72100_CLK_SCIF6 1 35*4882a593Smuzhiyun #define R7S72100_CLK_SCIF7 0 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* MSTP5 */ 38*4882a593Smuzhiyun #define R7S72100_CLK_SCI0 7 39*4882a593Smuzhiyun #define R7S72100_CLK_SCI1 6 40*4882a593Smuzhiyun #define R7S72100_CLK_SG0 5 41*4882a593Smuzhiyun #define R7S72100_CLK_SG1 4 42*4882a593Smuzhiyun #define R7S72100_CLK_SG2 3 43*4882a593Smuzhiyun #define R7S72100_CLK_SG3 2 44*4882a593Smuzhiyun #define R7S72100_CLK_OSTM0 1 45*4882a593Smuzhiyun #define R7S72100_CLK_OSTM1 0 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* MSTP6 */ 48*4882a593Smuzhiyun #define R7S72100_CLK_ADC 7 49*4882a593Smuzhiyun #define R7S72100_CLK_CEU 6 50*4882a593Smuzhiyun #define R7S72100_CLK_DOC0 5 51*4882a593Smuzhiyun #define R7S72100_CLK_DOC1 4 52*4882a593Smuzhiyun #define R7S72100_CLK_DRC0 3 53*4882a593Smuzhiyun #define R7S72100_CLK_DRC1 2 54*4882a593Smuzhiyun #define R7S72100_CLK_JCU 1 55*4882a593Smuzhiyun #define R7S72100_CLK_RTC 0 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* MSTP7 */ 58*4882a593Smuzhiyun #define R7S72100_CLK_VDEC0 7 59*4882a593Smuzhiyun #define R7S72100_CLK_VDEC1 6 60*4882a593Smuzhiyun #define R7S72100_CLK_ETHER 4 61*4882a593Smuzhiyun #define R7S72100_CLK_NAND 3 62*4882a593Smuzhiyun #define R7S72100_CLK_USB0 1 63*4882a593Smuzhiyun #define R7S72100_CLK_USB1 0 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* MSTP8 */ 66*4882a593Smuzhiyun #define R7S72100_CLK_IMR0 7 67*4882a593Smuzhiyun #define R7S72100_CLK_IMR1 6 68*4882a593Smuzhiyun #define R7S72100_CLK_IMRDISP 5 69*4882a593Smuzhiyun #define R7S72100_CLK_MMCIF 4 70*4882a593Smuzhiyun #define R7S72100_CLK_MLB 3 71*4882a593Smuzhiyun #define R7S72100_CLK_ETHAVB 2 72*4882a593Smuzhiyun #define R7S72100_CLK_SCUX 1 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* MSTP9 */ 75*4882a593Smuzhiyun #define R7S72100_CLK_I2C0 7 76*4882a593Smuzhiyun #define R7S72100_CLK_I2C1 6 77*4882a593Smuzhiyun #define R7S72100_CLK_I2C2 5 78*4882a593Smuzhiyun #define R7S72100_CLK_I2C3 4 79*4882a593Smuzhiyun #define R7S72100_CLK_SPIBSC0 3 80*4882a593Smuzhiyun #define R7S72100_CLK_SPIBSC1 2 81*4882a593Smuzhiyun #define R7S72100_CLK_VDC50 1 /* and LVDS */ 82*4882a593Smuzhiyun #define R7S72100_CLK_VDC51 0 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* MSTP10 */ 85*4882a593Smuzhiyun #define R7S72100_CLK_SPI0 7 86*4882a593Smuzhiyun #define R7S72100_CLK_SPI1 6 87*4882a593Smuzhiyun #define R7S72100_CLK_SPI2 5 88*4882a593Smuzhiyun #define R7S72100_CLK_SPI3 4 89*4882a593Smuzhiyun #define R7S72100_CLK_SPI4 3 90*4882a593Smuzhiyun #define R7S72100_CLK_CDROM 2 91*4882a593Smuzhiyun #define R7S72100_CLK_SPDIF 1 92*4882a593Smuzhiyun #define R7S72100_CLK_RGPVG2 0 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* MSTP11 */ 95*4882a593Smuzhiyun #define R7S72100_CLK_SSI0 5 96*4882a593Smuzhiyun #define R7S72100_CLK_SSI1 4 97*4882a593Smuzhiyun #define R7S72100_CLK_SSI2 3 98*4882a593Smuzhiyun #define R7S72100_CLK_SSI3 2 99*4882a593Smuzhiyun #define R7S72100_CLK_SSI4 1 100*4882a593Smuzhiyun #define R7S72100_CLK_SSI5 0 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* MSTP12 */ 103*4882a593Smuzhiyun #define R7S72100_CLK_SDHI00 3 104*4882a593Smuzhiyun #define R7S72100_CLK_SDHI01 2 105*4882a593Smuzhiyun #define R7S72100_CLK_SDHI10 1 106*4882a593Smuzhiyun #define R7S72100_CLK_SDHI11 0 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* MSTP13 */ 109*4882a593Smuzhiyun #define R7S72100_CLK_PIX1 2 110*4882a593Smuzhiyun #define R7S72100_CLK_PIX0 1 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */ 113