1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2015 Linaro Limited 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MSM_RPMCC_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* RPM clocks */ 10*4882a593Smuzhiyun #define RPM_PXO_CLK 0 11*4882a593Smuzhiyun #define RPM_PXO_A_CLK 1 12*4882a593Smuzhiyun #define RPM_CXO_CLK 2 13*4882a593Smuzhiyun #define RPM_CXO_A_CLK 3 14*4882a593Smuzhiyun #define RPM_APPS_FABRIC_CLK 4 15*4882a593Smuzhiyun #define RPM_APPS_FABRIC_A_CLK 5 16*4882a593Smuzhiyun #define RPM_CFPB_CLK 6 17*4882a593Smuzhiyun #define RPM_CFPB_A_CLK 7 18*4882a593Smuzhiyun #define RPM_QDSS_CLK 8 19*4882a593Smuzhiyun #define RPM_QDSS_A_CLK 9 20*4882a593Smuzhiyun #define RPM_DAYTONA_FABRIC_CLK 10 21*4882a593Smuzhiyun #define RPM_DAYTONA_FABRIC_A_CLK 11 22*4882a593Smuzhiyun #define RPM_EBI1_CLK 12 23*4882a593Smuzhiyun #define RPM_EBI1_A_CLK 13 24*4882a593Smuzhiyun #define RPM_MM_FABRIC_CLK 14 25*4882a593Smuzhiyun #define RPM_MM_FABRIC_A_CLK 15 26*4882a593Smuzhiyun #define RPM_MMFPB_CLK 16 27*4882a593Smuzhiyun #define RPM_MMFPB_A_CLK 17 28*4882a593Smuzhiyun #define RPM_SYS_FABRIC_CLK 18 29*4882a593Smuzhiyun #define RPM_SYS_FABRIC_A_CLK 19 30*4882a593Smuzhiyun #define RPM_SFPB_CLK 20 31*4882a593Smuzhiyun #define RPM_SFPB_A_CLK 21 32*4882a593Smuzhiyun #define RPM_SMI_CLK 22 33*4882a593Smuzhiyun #define RPM_SMI_A_CLK 23 34*4882a593Smuzhiyun #define RPM_PLL4_CLK 24 35*4882a593Smuzhiyun #define RPM_XO_D0 25 36*4882a593Smuzhiyun #define RPM_XO_D1 26 37*4882a593Smuzhiyun #define RPM_XO_A0 27 38*4882a593Smuzhiyun #define RPM_XO_A1 28 39*4882a593Smuzhiyun #define RPM_XO_A2 29 40*4882a593Smuzhiyun #define RPM_NSS_FABRIC_0_CLK 30 41*4882a593Smuzhiyun #define RPM_NSS_FABRIC_0_A_CLK 31 42*4882a593Smuzhiyun #define RPM_NSS_FABRIC_1_CLK 32 43*4882a593Smuzhiyun #define RPM_NSS_FABRIC_1_A_CLK 33 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* SMD RPM clocks */ 46*4882a593Smuzhiyun #define RPM_SMD_XO_CLK_SRC 0 47*4882a593Smuzhiyun #define RPM_SMD_XO_A_CLK_SRC 1 48*4882a593Smuzhiyun #define RPM_SMD_PCNOC_CLK 2 49*4882a593Smuzhiyun #define RPM_SMD_PCNOC_A_CLK 3 50*4882a593Smuzhiyun #define RPM_SMD_SNOC_CLK 4 51*4882a593Smuzhiyun #define RPM_SMD_SNOC_A_CLK 5 52*4882a593Smuzhiyun #define RPM_SMD_BIMC_CLK 6 53*4882a593Smuzhiyun #define RPM_SMD_BIMC_A_CLK 7 54*4882a593Smuzhiyun #define RPM_SMD_QDSS_CLK 8 55*4882a593Smuzhiyun #define RPM_SMD_QDSS_A_CLK 9 56*4882a593Smuzhiyun #define RPM_SMD_BB_CLK1 10 57*4882a593Smuzhiyun #define RPM_SMD_BB_CLK1_A 11 58*4882a593Smuzhiyun #define RPM_SMD_BB_CLK2 12 59*4882a593Smuzhiyun #define RPM_SMD_BB_CLK2_A 13 60*4882a593Smuzhiyun #define RPM_SMD_RF_CLK1 14 61*4882a593Smuzhiyun #define RPM_SMD_RF_CLK1_A 15 62*4882a593Smuzhiyun #define RPM_SMD_RF_CLK2 16 63*4882a593Smuzhiyun #define RPM_SMD_RF_CLK2_A 17 64*4882a593Smuzhiyun #define RPM_SMD_BB_CLK1_PIN 18 65*4882a593Smuzhiyun #define RPM_SMD_BB_CLK1_A_PIN 19 66*4882a593Smuzhiyun #define RPM_SMD_BB_CLK2_PIN 20 67*4882a593Smuzhiyun #define RPM_SMD_BB_CLK2_A_PIN 21 68*4882a593Smuzhiyun #define RPM_SMD_RF_CLK1_PIN 22 69*4882a593Smuzhiyun #define RPM_SMD_RF_CLK1_A_PIN 23 70*4882a593Smuzhiyun #define RPM_SMD_RF_CLK2_PIN 24 71*4882a593Smuzhiyun #define RPM_SMD_RF_CLK2_A_PIN 25 72*4882a593Smuzhiyun #define RPM_SMD_PNOC_CLK 26 73*4882a593Smuzhiyun #define RPM_SMD_PNOC_A_CLK 27 74*4882a593Smuzhiyun #define RPM_SMD_CNOC_CLK 28 75*4882a593Smuzhiyun #define RPM_SMD_CNOC_A_CLK 29 76*4882a593Smuzhiyun #define RPM_SMD_MMSSNOC_AHB_CLK 30 77*4882a593Smuzhiyun #define RPM_SMD_MMSSNOC_AHB_A_CLK 31 78*4882a593Smuzhiyun #define RPM_SMD_GFX3D_CLK_SRC 32 79*4882a593Smuzhiyun #define RPM_SMD_GFX3D_A_CLK_SRC 33 80*4882a593Smuzhiyun #define RPM_SMD_OCMEMGX_CLK 34 81*4882a593Smuzhiyun #define RPM_SMD_OCMEMGX_A_CLK 35 82*4882a593Smuzhiyun #define RPM_SMD_CXO_D0 36 83*4882a593Smuzhiyun #define RPM_SMD_CXO_D0_A 37 84*4882a593Smuzhiyun #define RPM_SMD_CXO_D1 38 85*4882a593Smuzhiyun #define RPM_SMD_CXO_D1_A 39 86*4882a593Smuzhiyun #define RPM_SMD_CXO_A0 40 87*4882a593Smuzhiyun #define RPM_SMD_CXO_A0_A 41 88*4882a593Smuzhiyun #define RPM_SMD_CXO_A1 42 89*4882a593Smuzhiyun #define RPM_SMD_CXO_A1_A 43 90*4882a593Smuzhiyun #define RPM_SMD_CXO_A2 44 91*4882a593Smuzhiyun #define RPM_SMD_CXO_A2_A 45 92*4882a593Smuzhiyun #define RPM_SMD_DIV_CLK1 46 93*4882a593Smuzhiyun #define RPM_SMD_DIV_A_CLK1 47 94*4882a593Smuzhiyun #define RPM_SMD_DIV_CLK2 48 95*4882a593Smuzhiyun #define RPM_SMD_DIV_A_CLK2 49 96*4882a593Smuzhiyun #define RPM_SMD_DIFF_CLK 50 97*4882a593Smuzhiyun #define RPM_SMD_DIFF_A_CLK 51 98*4882a593Smuzhiyun #define RPM_SMD_CXO_D0_PIN 52 99*4882a593Smuzhiyun #define RPM_SMD_CXO_D0_A_PIN 53 100*4882a593Smuzhiyun #define RPM_SMD_CXO_D1_PIN 54 101*4882a593Smuzhiyun #define RPM_SMD_CXO_D1_A_PIN 55 102*4882a593Smuzhiyun #define RPM_SMD_CXO_A0_PIN 56 103*4882a593Smuzhiyun #define RPM_SMD_CXO_A0_A_PIN 57 104*4882a593Smuzhiyun #define RPM_SMD_CXO_A1_PIN 58 105*4882a593Smuzhiyun #define RPM_SMD_CXO_A1_A_PIN 59 106*4882a593Smuzhiyun #define RPM_SMD_CXO_A2_PIN 60 107*4882a593Smuzhiyun #define RPM_SMD_CXO_A2_A_PIN 61 108*4882a593Smuzhiyun #define RPM_SMD_AGGR1_NOC_CLK 62 109*4882a593Smuzhiyun #define RPM_SMD_AGGR1_NOC_A_CLK 63 110*4882a593Smuzhiyun #define RPM_SMD_AGGR2_NOC_CLK 64 111*4882a593Smuzhiyun #define RPM_SMD_AGGR2_NOC_A_CLK 65 112*4882a593Smuzhiyun #define RPM_SMD_MMAXI_CLK 66 113*4882a593Smuzhiyun #define RPM_SMD_MMAXI_A_CLK 67 114*4882a593Smuzhiyun #define RPM_SMD_IPA_CLK 68 115*4882a593Smuzhiyun #define RPM_SMD_IPA_A_CLK 69 116*4882a593Smuzhiyun #define RPM_SMD_CE1_CLK 70 117*4882a593Smuzhiyun #define RPM_SMD_CE1_A_CLK 71 118*4882a593Smuzhiyun #define RPM_SMD_DIV_CLK3 72 119*4882a593Smuzhiyun #define RPM_SMD_DIV_A_CLK3 73 120*4882a593Smuzhiyun #define RPM_SMD_LN_BB_CLK 74 121*4882a593Smuzhiyun #define RPM_SMD_LN_BB_A_CLK 75 122*4882a593Smuzhiyun #define RPM_SMD_BIMC_GPU_CLK 76 123*4882a593Smuzhiyun #define RPM_SMD_BIMC_GPU_A_CLK 77 124*4882a593Smuzhiyun #define RPM_SMD_QPIC_CLK 78 125*4882a593Smuzhiyun #define RPM_SMD_QPIC_CLK_A 79 126*4882a593Smuzhiyun #define RPM_SMD_LN_BB_CLK1 80 127*4882a593Smuzhiyun #define RPM_SMD_LN_BB_CLK1_A 81 128*4882a593Smuzhiyun #define RPM_SMD_LN_BB_CLK2 82 129*4882a593Smuzhiyun #define RPM_SMD_LN_BB_CLK2_A 83 130*4882a593Smuzhiyun #define RPM_SMD_LN_BB_CLK3_PIN 84 131*4882a593Smuzhiyun #define RPM_SMD_LN_BB_CLK3_A_PIN 85 132*4882a593Smuzhiyun #define RPM_SMD_RF_CLK3 86 133*4882a593Smuzhiyun #define RPM_SMD_RF_CLK3_A 87 134*4882a593Smuzhiyun #define RPM_SMD_RF_CLK3_PIN 88 135*4882a593Smuzhiyun #define RPM_SMD_RF_CLK3_A_PIN 89 136*4882a593Smuzhiyun #define RPM_SMD_MMSSNOC_AXI_CLK 90 137*4882a593Smuzhiyun #define RPM_SMD_MMSSNOC_AXI_CLK_A 91 138*4882a593Smuzhiyun #define RPM_SMD_CNOC_PERIPH_CLK 92 139*4882a593Smuzhiyun #define RPM_SMD_CNOC_PERIPH_A_CLK 93 140*4882a593Smuzhiyun #define RPM_SMD_LN_BB_CLK3 94 141*4882a593Smuzhiyun #define RPM_SMD_LN_BB_CLK3_A 95 142*4882a593Smuzhiyun #define RPM_SMD_LN_BB_CLK1_PIN 96 143*4882a593Smuzhiyun #define RPM_SMD_LN_BB_CLK1_A_PIN 97 144*4882a593Smuzhiyun #define RPM_SMD_LN_BB_CLK2_PIN 98 145*4882a593Smuzhiyun #define RPM_SMD_LN_BB_CLK2_A_PIN 99 146*4882a593Smuzhiyun #define RPM_SMD_SYSMMNOC_CLK 100 147*4882a593Smuzhiyun #define RPM_SMD_SYSMMNOC_A_CLK 101 148*4882a593Smuzhiyun #define RPM_SMD_CE2_CLK 102 149*4882a593Smuzhiyun #define RPM_SMD_CE2_A_CLK 103 150*4882a593Smuzhiyun #define RPM_SMD_CE3_CLK 104 151*4882a593Smuzhiyun #define RPM_SMD_CE3_A_CLK 105 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun #endif 154