1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MSM_MMCC_8960_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MSM_MMCC_8960_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define MMSS_AHB_SRC 0 10*4882a593Smuzhiyun #define FAB_AHB_CLK 1 11*4882a593Smuzhiyun #define APU_AHB_CLK 2 12*4882a593Smuzhiyun #define TV_ENC_AHB_CLK 3 13*4882a593Smuzhiyun #define AMP_AHB_CLK 4 14*4882a593Smuzhiyun #define DSI2_S_AHB_CLK 5 15*4882a593Smuzhiyun #define JPEGD_AHB_CLK 6 16*4882a593Smuzhiyun #define GFX2D0_AHB_CLK 7 17*4882a593Smuzhiyun #define DSI_S_AHB_CLK 8 18*4882a593Smuzhiyun #define DSI2_M_AHB_CLK 9 19*4882a593Smuzhiyun #define VPE_AHB_CLK 10 20*4882a593Smuzhiyun #define SMMU_AHB_CLK 11 21*4882a593Smuzhiyun #define HDMI_M_AHB_CLK 12 22*4882a593Smuzhiyun #define VFE_AHB_CLK 13 23*4882a593Smuzhiyun #define ROT_AHB_CLK 14 24*4882a593Smuzhiyun #define VCODEC_AHB_CLK 15 25*4882a593Smuzhiyun #define MDP_AHB_CLK 16 26*4882a593Smuzhiyun #define DSI_M_AHB_CLK 17 27*4882a593Smuzhiyun #define CSI_AHB_CLK 18 28*4882a593Smuzhiyun #define MMSS_IMEM_AHB_CLK 19 29*4882a593Smuzhiyun #define IJPEG_AHB_CLK 20 30*4882a593Smuzhiyun #define HDMI_S_AHB_CLK 21 31*4882a593Smuzhiyun #define GFX3D_AHB_CLK 22 32*4882a593Smuzhiyun #define GFX2D1_AHB_CLK 23 33*4882a593Smuzhiyun #define MMSS_FPB_CLK 24 34*4882a593Smuzhiyun #define MMSS_AXI_SRC 25 35*4882a593Smuzhiyun #define MMSS_FAB_CORE 26 36*4882a593Smuzhiyun #define FAB_MSP_AXI_CLK 27 37*4882a593Smuzhiyun #define JPEGD_AXI_CLK 28 38*4882a593Smuzhiyun #define GMEM_AXI_CLK 29 39*4882a593Smuzhiyun #define MDP_AXI_CLK 30 40*4882a593Smuzhiyun #define MMSS_IMEM_AXI_CLK 31 41*4882a593Smuzhiyun #define IJPEG_AXI_CLK 32 42*4882a593Smuzhiyun #define GFX3D_AXI_CLK 33 43*4882a593Smuzhiyun #define VCODEC_AXI_CLK 34 44*4882a593Smuzhiyun #define VFE_AXI_CLK 35 45*4882a593Smuzhiyun #define VPE_AXI_CLK 36 46*4882a593Smuzhiyun #define ROT_AXI_CLK 37 47*4882a593Smuzhiyun #define VCODEC_AXI_A_CLK 38 48*4882a593Smuzhiyun #define VCODEC_AXI_B_CLK 39 49*4882a593Smuzhiyun #define MM_AXI_S3_FCLK 40 50*4882a593Smuzhiyun #define MM_AXI_S2_FCLK 41 51*4882a593Smuzhiyun #define MM_AXI_S1_FCLK 42 52*4882a593Smuzhiyun #define MM_AXI_S0_FCLK 43 53*4882a593Smuzhiyun #define MM_AXI_S2_CLK 44 54*4882a593Smuzhiyun #define MM_AXI_S1_CLK 45 55*4882a593Smuzhiyun #define MM_AXI_S0_CLK 46 56*4882a593Smuzhiyun #define CSI0_SRC 47 57*4882a593Smuzhiyun #define CSI0_CLK 48 58*4882a593Smuzhiyun #define CSI0_PHY_CLK 49 59*4882a593Smuzhiyun #define CSI1_SRC 50 60*4882a593Smuzhiyun #define CSI1_CLK 51 61*4882a593Smuzhiyun #define CSI1_PHY_CLK 52 62*4882a593Smuzhiyun #define CSI2_SRC 53 63*4882a593Smuzhiyun #define CSI2_CLK 54 64*4882a593Smuzhiyun #define CSI2_PHY_CLK 55 65*4882a593Smuzhiyun #define DSI_SRC 56 66*4882a593Smuzhiyun #define DSI_CLK 57 67*4882a593Smuzhiyun #define CSI_PIX_CLK 58 68*4882a593Smuzhiyun #define CSI_RDI_CLK 59 69*4882a593Smuzhiyun #define MDP_VSYNC_CLK 60 70*4882a593Smuzhiyun #define HDMI_DIV_CLK 61 71*4882a593Smuzhiyun #define HDMI_APP_CLK 62 72*4882a593Smuzhiyun #define CSI_PIX1_CLK 63 73*4882a593Smuzhiyun #define CSI_RDI2_CLK 64 74*4882a593Smuzhiyun #define CSI_RDI1_CLK 65 75*4882a593Smuzhiyun #define GFX2D0_SRC 66 76*4882a593Smuzhiyun #define GFX2D0_CLK 67 77*4882a593Smuzhiyun #define GFX2D1_SRC 68 78*4882a593Smuzhiyun #define GFX2D1_CLK 69 79*4882a593Smuzhiyun #define GFX3D_SRC 70 80*4882a593Smuzhiyun #define GFX3D_CLK 71 81*4882a593Smuzhiyun #define IJPEG_SRC 72 82*4882a593Smuzhiyun #define IJPEG_CLK 73 83*4882a593Smuzhiyun #define JPEGD_SRC 74 84*4882a593Smuzhiyun #define JPEGD_CLK 75 85*4882a593Smuzhiyun #define MDP_SRC 76 86*4882a593Smuzhiyun #define MDP_CLK 77 87*4882a593Smuzhiyun #define MDP_LUT_CLK 78 88*4882a593Smuzhiyun #define DSI2_PIXEL_SRC 79 89*4882a593Smuzhiyun #define DSI2_PIXEL_CLK 80 90*4882a593Smuzhiyun #define DSI2_SRC 81 91*4882a593Smuzhiyun #define DSI2_CLK 82 92*4882a593Smuzhiyun #define DSI1_BYTE_SRC 83 93*4882a593Smuzhiyun #define DSI1_BYTE_CLK 84 94*4882a593Smuzhiyun #define DSI2_BYTE_SRC 85 95*4882a593Smuzhiyun #define DSI2_BYTE_CLK 86 96*4882a593Smuzhiyun #define DSI1_ESC_SRC 87 97*4882a593Smuzhiyun #define DSI1_ESC_CLK 88 98*4882a593Smuzhiyun #define DSI2_ESC_SRC 89 99*4882a593Smuzhiyun #define DSI2_ESC_CLK 90 100*4882a593Smuzhiyun #define ROT_SRC 91 101*4882a593Smuzhiyun #define ROT_CLK 92 102*4882a593Smuzhiyun #define TV_ENC_CLK 93 103*4882a593Smuzhiyun #define TV_DAC_CLK 94 104*4882a593Smuzhiyun #define HDMI_TV_CLK 95 105*4882a593Smuzhiyun #define MDP_TV_CLK 96 106*4882a593Smuzhiyun #define TV_SRC 97 107*4882a593Smuzhiyun #define VCODEC_SRC 98 108*4882a593Smuzhiyun #define VCODEC_CLK 99 109*4882a593Smuzhiyun #define VFE_SRC 100 110*4882a593Smuzhiyun #define VFE_CLK 101 111*4882a593Smuzhiyun #define VFE_CSI_CLK 102 112*4882a593Smuzhiyun #define VPE_SRC 103 113*4882a593Smuzhiyun #define VPE_CLK 104 114*4882a593Smuzhiyun #define DSI_PIXEL_SRC 105 115*4882a593Smuzhiyun #define DSI_PIXEL_CLK 106 116*4882a593Smuzhiyun #define CAMCLK0_SRC 107 117*4882a593Smuzhiyun #define CAMCLK0_CLK 108 118*4882a593Smuzhiyun #define CAMCLK1_SRC 109 119*4882a593Smuzhiyun #define CAMCLK1_CLK 110 120*4882a593Smuzhiyun #define CAMCLK2_SRC 111 121*4882a593Smuzhiyun #define CAMCLK2_CLK 112 122*4882a593Smuzhiyun #define CSIPHYTIMER_SRC 113 123*4882a593Smuzhiyun #define CSIPHY2_TIMER_CLK 114 124*4882a593Smuzhiyun #define CSIPHY1_TIMER_CLK 115 125*4882a593Smuzhiyun #define CSIPHY0_TIMER_CLK 116 126*4882a593Smuzhiyun #define PLL1 117 127*4882a593Smuzhiyun #define PLL2 118 128*4882a593Smuzhiyun #define RGB_TV_CLK 119 129*4882a593Smuzhiyun #define NPL_TV_CLK 120 130*4882a593Smuzhiyun #define VCAP_AHB_CLK 121 131*4882a593Smuzhiyun #define VCAP_AXI_CLK 122 132*4882a593Smuzhiyun #define VCAP_SRC 123 133*4882a593Smuzhiyun #define VCAP_CLK 124 134*4882a593Smuzhiyun #define VCAP_NPL_CLK 125 135*4882a593Smuzhiyun #define PLL15 126 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #endif 138