xref: /OK3568_Linux_fs/kernel/include/dt-bindings/clock/qcom,lcc-msm8960.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_LCC_MSM8960_H
7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_LCC_MSM8960_H
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #define PLL4				0
10*4882a593Smuzhiyun #define MI2S_OSR_SRC			1
11*4882a593Smuzhiyun #define MI2S_OSR_CLK			2
12*4882a593Smuzhiyun #define MI2S_DIV_CLK			3
13*4882a593Smuzhiyun #define MI2S_BIT_DIV_CLK		4
14*4882a593Smuzhiyun #define MI2S_BIT_CLK			5
15*4882a593Smuzhiyun #define PCM_SRC				6
16*4882a593Smuzhiyun #define PCM_CLK_OUT			7
17*4882a593Smuzhiyun #define PCM_CLK				8
18*4882a593Smuzhiyun #define SLIMBUS_SRC			9
19*4882a593Smuzhiyun #define AUDIO_SLIMBUS_CLK		10
20*4882a593Smuzhiyun #define SPS_SLIMBUS_CLK			11
21*4882a593Smuzhiyun #define CODEC_I2S_MIC_OSR_SRC		12
22*4882a593Smuzhiyun #define CODEC_I2S_MIC_OSR_CLK		13
23*4882a593Smuzhiyun #define CODEC_I2S_MIC_DIV_CLK		14
24*4882a593Smuzhiyun #define CODEC_I2S_MIC_BIT_DIV_CLK	15
25*4882a593Smuzhiyun #define CODEC_I2S_MIC_BIT_CLK		16
26*4882a593Smuzhiyun #define SPARE_I2S_MIC_OSR_SRC		17
27*4882a593Smuzhiyun #define SPARE_I2S_MIC_OSR_CLK		18
28*4882a593Smuzhiyun #define SPARE_I2S_MIC_DIV_CLK		19
29*4882a593Smuzhiyun #define SPARE_I2S_MIC_BIT_DIV_CLK	20
30*4882a593Smuzhiyun #define SPARE_I2S_MIC_BIT_CLK		21
31*4882a593Smuzhiyun #define CODEC_I2S_SPKR_OSR_SRC		22
32*4882a593Smuzhiyun #define CODEC_I2S_SPKR_OSR_CLK		23
33*4882a593Smuzhiyun #define CODEC_I2S_SPKR_DIV_CLK		24
34*4882a593Smuzhiyun #define CODEC_I2S_SPKR_BIT_DIV_CLK	25
35*4882a593Smuzhiyun #define CODEC_I2S_SPKR_BIT_CLK		26
36*4882a593Smuzhiyun #define SPARE_I2S_SPKR_OSR_SRC		27
37*4882a593Smuzhiyun #define SPARE_I2S_SPKR_OSR_CLK		28
38*4882a593Smuzhiyun #define SPARE_I2S_SPKR_DIV_CLK		29
39*4882a593Smuzhiyun #define SPARE_I2S_SPKR_BIT_DIV_CLK	30
40*4882a593Smuzhiyun #define SPARE_I2S_SPKR_BIT_CLK		31
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun #endif
43