1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8250_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* GPU_CC clock registers */ 10*4882a593Smuzhiyun #define GPU_CC_AHB_CLK 0 11*4882a593Smuzhiyun #define GPU_CC_CRC_AHB_CLK 1 12*4882a593Smuzhiyun #define GPU_CC_CX_APB_CLK 2 13*4882a593Smuzhiyun #define GPU_CC_CX_GMU_CLK 3 14*4882a593Smuzhiyun #define GPU_CC_CX_SNOC_DVM_CLK 4 15*4882a593Smuzhiyun #define GPU_CC_CXO_AON_CLK 5 16*4882a593Smuzhiyun #define GPU_CC_CXO_CLK 6 17*4882a593Smuzhiyun #define GPU_CC_GMU_CLK_SRC 7 18*4882a593Smuzhiyun #define GPU_CC_GX_GMU_CLK 8 19*4882a593Smuzhiyun #define GPU_CC_PLL1 9 20*4882a593Smuzhiyun #define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 10 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* GPU_CC Resets */ 23*4882a593Smuzhiyun #define GPUCC_GPU_CC_ACD_BCR 0 24*4882a593Smuzhiyun #define GPUCC_GPU_CC_CX_BCR 1 25*4882a593Smuzhiyun #define GPUCC_GPU_CC_GFX3D_AON_BCR 2 26*4882a593Smuzhiyun #define GPUCC_GPU_CC_GMU_BCR 3 27*4882a593Smuzhiyun #define GPUCC_GPU_CC_GX_BCR 4 28*4882a593Smuzhiyun #define GPUCC_GPU_CC_XO_BCR 5 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* GPU_CC GDSCRs */ 31*4882a593Smuzhiyun #define GPU_CX_GDSC 0 32*4882a593Smuzhiyun #define GPU_GX_GDSC 1 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #endif 35