1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019, Jeffrey Hugo 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MSM_GPUCC_8998_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MSM_GPUCC_8998_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define GPUPLL0 0 10*4882a593Smuzhiyun #define GPUPLL0_OUT_EVEN 1 11*4882a593Smuzhiyun #define RBCPR_CLK_SRC 2 12*4882a593Smuzhiyun #define GFX3D_CLK_SRC 3 13*4882a593Smuzhiyun #define RBBMTIMER_CLK_SRC 4 14*4882a593Smuzhiyun #define GFX3D_ISENSE_CLK_SRC 5 15*4882a593Smuzhiyun #define RBCPR_CLK 6 16*4882a593Smuzhiyun #define GFX3D_CLK 7 17*4882a593Smuzhiyun #define RBBMTIMER_CLK 8 18*4882a593Smuzhiyun #define GFX3D_ISENSE_CLK 9 19*4882a593Smuzhiyun #define GPUCC_CXO_CLK 10 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define GPU_CX_BCR 0 22*4882a593Smuzhiyun #define RBCPR_BCR 1 23*4882a593Smuzhiyun #define GPU_GX_BCR 2 24*4882a593Smuzhiyun #define GPU_ISENSE_BCR 3 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define GPU_CX_GDSC 1 27*4882a593Smuzhiyun #define GPU_GX_GDSC 2 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #endif 30