1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* GCC clock registers */ 10*4882a593Smuzhiyun #define GCC_AGGRE_NOC_PCIE_TBU_CLK 0 11*4882a593Smuzhiyun #define GCC_AGGRE_UFS_CARD_AXI_CLK 1 12*4882a593Smuzhiyun #define GCC_AGGRE_UFS_PHY_AXI_CLK 2 13*4882a593Smuzhiyun #define GCC_AGGRE_USB3_PRIM_AXI_CLK 3 14*4882a593Smuzhiyun #define GCC_AGGRE_USB3_SEC_AXI_CLK 4 15*4882a593Smuzhiyun #define GCC_BOOT_ROM_AHB_CLK 5 16*4882a593Smuzhiyun #define GCC_CAMERA_AHB_CLK 6 17*4882a593Smuzhiyun #define GCC_CAMERA_AXI_CLK 7 18*4882a593Smuzhiyun #define GCC_CAMERA_XO_CLK 8 19*4882a593Smuzhiyun #define GCC_CE1_AHB_CLK 9 20*4882a593Smuzhiyun #define GCC_CE1_AXI_CLK 10 21*4882a593Smuzhiyun #define GCC_CE1_CLK 11 22*4882a593Smuzhiyun #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12 23*4882a593Smuzhiyun #define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13 24*4882a593Smuzhiyun #define GCC_CPUSS_AHB_CLK 14 25*4882a593Smuzhiyun #define GCC_CPUSS_AHB_CLK_SRC 15 26*4882a593Smuzhiyun #define GCC_CPUSS_RBCPR_CLK 16 27*4882a593Smuzhiyun #define GCC_CPUSS_RBCPR_CLK_SRC 17 28*4882a593Smuzhiyun #define GCC_DDRSS_GPU_AXI_CLK 18 29*4882a593Smuzhiyun #define GCC_DISP_AHB_CLK 19 30*4882a593Smuzhiyun #define GCC_DISP_AXI_CLK 20 31*4882a593Smuzhiyun #define GCC_DISP_GPLL0_CLK_SRC 21 32*4882a593Smuzhiyun #define GCC_DISP_GPLL0_DIV_CLK_SRC 22 33*4882a593Smuzhiyun #define GCC_DISP_XO_CLK 23 34*4882a593Smuzhiyun #define GCC_GP1_CLK 24 35*4882a593Smuzhiyun #define GCC_GP1_CLK_SRC 25 36*4882a593Smuzhiyun #define GCC_GP2_CLK 26 37*4882a593Smuzhiyun #define GCC_GP2_CLK_SRC 27 38*4882a593Smuzhiyun #define GCC_GP3_CLK 28 39*4882a593Smuzhiyun #define GCC_GP3_CLK_SRC 29 40*4882a593Smuzhiyun #define GCC_GPU_CFG_AHB_CLK 30 41*4882a593Smuzhiyun #define GCC_GPU_GPLL0_CLK_SRC 31 42*4882a593Smuzhiyun #define GCC_GPU_GPLL0_DIV_CLK_SRC 32 43*4882a593Smuzhiyun #define GCC_GPU_MEMNOC_GFX_CLK 33 44*4882a593Smuzhiyun #define GCC_GPU_SNOC_DVM_GFX_CLK 34 45*4882a593Smuzhiyun #define GCC_MSS_AXIS2_CLK 35 46*4882a593Smuzhiyun #define GCC_MSS_CFG_AHB_CLK 36 47*4882a593Smuzhiyun #define GCC_MSS_GPLL0_DIV_CLK_SRC 37 48*4882a593Smuzhiyun #define GCC_MSS_MFAB_AXIS_CLK 38 49*4882a593Smuzhiyun #define GCC_MSS_Q6_MEMNOC_AXI_CLK 39 50*4882a593Smuzhiyun #define GCC_MSS_SNOC_AXI_CLK 40 51*4882a593Smuzhiyun #define GCC_PCIE_0_AUX_CLK 41 52*4882a593Smuzhiyun #define GCC_PCIE_0_AUX_CLK_SRC 42 53*4882a593Smuzhiyun #define GCC_PCIE_0_CFG_AHB_CLK 43 54*4882a593Smuzhiyun #define GCC_PCIE_0_CLKREF_CLK 44 55*4882a593Smuzhiyun #define GCC_PCIE_0_MSTR_AXI_CLK 45 56*4882a593Smuzhiyun #define GCC_PCIE_0_PIPE_CLK 46 57*4882a593Smuzhiyun #define GCC_PCIE_0_SLV_AXI_CLK 47 58*4882a593Smuzhiyun #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48 59*4882a593Smuzhiyun #define GCC_PCIE_1_AUX_CLK 49 60*4882a593Smuzhiyun #define GCC_PCIE_1_AUX_CLK_SRC 50 61*4882a593Smuzhiyun #define GCC_PCIE_1_CFG_AHB_CLK 51 62*4882a593Smuzhiyun #define GCC_PCIE_1_CLKREF_CLK 52 63*4882a593Smuzhiyun #define GCC_PCIE_1_MSTR_AXI_CLK 53 64*4882a593Smuzhiyun #define GCC_PCIE_1_PIPE_CLK 54 65*4882a593Smuzhiyun #define GCC_PCIE_1_SLV_AXI_CLK 55 66*4882a593Smuzhiyun #define GCC_PCIE_1_SLV_Q2A_AXI_CLK 56 67*4882a593Smuzhiyun #define GCC_PCIE_PHY_AUX_CLK 57 68*4882a593Smuzhiyun #define GCC_PCIE_PHY_REFGEN_CLK 58 69*4882a593Smuzhiyun #define GCC_PCIE_PHY_REFGEN_CLK_SRC 59 70*4882a593Smuzhiyun #define GCC_PDM2_CLK 60 71*4882a593Smuzhiyun #define GCC_PDM2_CLK_SRC 61 72*4882a593Smuzhiyun #define GCC_PDM_AHB_CLK 62 73*4882a593Smuzhiyun #define GCC_PDM_XO4_CLK 63 74*4882a593Smuzhiyun #define GCC_PRNG_AHB_CLK 64 75*4882a593Smuzhiyun #define GCC_QMIP_CAMERA_AHB_CLK 65 76*4882a593Smuzhiyun #define GCC_QMIP_DISP_AHB_CLK 66 77*4882a593Smuzhiyun #define GCC_QMIP_VIDEO_AHB_CLK 67 78*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S0_CLK 68 79*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S0_CLK_SRC 69 80*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S1_CLK 70 81*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S1_CLK_SRC 71 82*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S2_CLK 72 83*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S2_CLK_SRC 73 84*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S3_CLK 74 85*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S3_CLK_SRC 75 86*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S4_CLK 76 87*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S4_CLK_SRC 77 88*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S5_CLK 78 89*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S5_CLK_SRC 79 90*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S6_CLK 80 91*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S6_CLK_SRC 81 92*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S7_CLK 82 93*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S7_CLK_SRC 83 94*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S0_CLK 84 95*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S0_CLK_SRC 85 96*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S1_CLK 86 97*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S1_CLK_SRC 87 98*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S2_CLK 88 99*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S2_CLK_SRC 89 100*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S3_CLK 90 101*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S3_CLK_SRC 91 102*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S4_CLK 92 103*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S4_CLK_SRC 93 104*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S5_CLK 94 105*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S5_CLK_SRC 95 106*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S6_CLK 96 107*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S6_CLK_SRC 97 108*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S7_CLK 98 109*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S7_CLK_SRC 99 110*4882a593Smuzhiyun #define GCC_QUPV3_WRAP_0_M_AHB_CLK 100 111*4882a593Smuzhiyun #define GCC_QUPV3_WRAP_0_S_AHB_CLK 101 112*4882a593Smuzhiyun #define GCC_QUPV3_WRAP_1_M_AHB_CLK 102 113*4882a593Smuzhiyun #define GCC_QUPV3_WRAP_1_S_AHB_CLK 103 114*4882a593Smuzhiyun #define GCC_SDCC2_AHB_CLK 104 115*4882a593Smuzhiyun #define GCC_SDCC2_APPS_CLK 105 116*4882a593Smuzhiyun #define GCC_SDCC2_APPS_CLK_SRC 106 117*4882a593Smuzhiyun #define GCC_SDCC4_AHB_CLK 107 118*4882a593Smuzhiyun #define GCC_SDCC4_APPS_CLK 108 119*4882a593Smuzhiyun #define GCC_SDCC4_APPS_CLK_SRC 109 120*4882a593Smuzhiyun #define GCC_SYS_NOC_CPUSS_AHB_CLK 110 121*4882a593Smuzhiyun #define GCC_TSIF_AHB_CLK 111 122*4882a593Smuzhiyun #define GCC_TSIF_INACTIVITY_TIMERS_CLK 112 123*4882a593Smuzhiyun #define GCC_TSIF_REF_CLK 113 124*4882a593Smuzhiyun #define GCC_TSIF_REF_CLK_SRC 114 125*4882a593Smuzhiyun #define GCC_UFS_CARD_AHB_CLK 115 126*4882a593Smuzhiyun #define GCC_UFS_CARD_AXI_CLK 116 127*4882a593Smuzhiyun #define GCC_UFS_CARD_AXI_CLK_SRC 117 128*4882a593Smuzhiyun #define GCC_UFS_CARD_CLKREF_CLK 118 129*4882a593Smuzhiyun #define GCC_UFS_CARD_ICE_CORE_CLK 119 130*4882a593Smuzhiyun #define GCC_UFS_CARD_ICE_CORE_CLK_SRC 120 131*4882a593Smuzhiyun #define GCC_UFS_CARD_PHY_AUX_CLK 121 132*4882a593Smuzhiyun #define GCC_UFS_CARD_PHY_AUX_CLK_SRC 122 133*4882a593Smuzhiyun #define GCC_UFS_CARD_RX_SYMBOL_0_CLK 123 134*4882a593Smuzhiyun #define GCC_UFS_CARD_RX_SYMBOL_1_CLK 124 135*4882a593Smuzhiyun #define GCC_UFS_CARD_TX_SYMBOL_0_CLK 125 136*4882a593Smuzhiyun #define GCC_UFS_CARD_UNIPRO_CORE_CLK 126 137*4882a593Smuzhiyun #define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 127 138*4882a593Smuzhiyun #define GCC_UFS_MEM_CLKREF_CLK 128 139*4882a593Smuzhiyun #define GCC_UFS_PHY_AHB_CLK 129 140*4882a593Smuzhiyun #define GCC_UFS_PHY_AXI_CLK 130 141*4882a593Smuzhiyun #define GCC_UFS_PHY_AXI_CLK_SRC 131 142*4882a593Smuzhiyun #define GCC_UFS_PHY_ICE_CORE_CLK 132 143*4882a593Smuzhiyun #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 133 144*4882a593Smuzhiyun #define GCC_UFS_PHY_PHY_AUX_CLK 134 145*4882a593Smuzhiyun #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 135 146*4882a593Smuzhiyun #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 136 147*4882a593Smuzhiyun #define GCC_UFS_PHY_RX_SYMBOL_1_CLK 137 148*4882a593Smuzhiyun #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138 149*4882a593Smuzhiyun #define GCC_UFS_PHY_UNIPRO_CORE_CLK 139 150*4882a593Smuzhiyun #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 140 151*4882a593Smuzhiyun #define GCC_USB30_PRIM_MASTER_CLK 141 152*4882a593Smuzhiyun #define GCC_USB30_PRIM_MASTER_CLK_SRC 142 153*4882a593Smuzhiyun #define GCC_USB30_PRIM_MOCK_UTMI_CLK 143 154*4882a593Smuzhiyun #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 144 155*4882a593Smuzhiyun #define GCC_USB30_PRIM_SLEEP_CLK 145 156*4882a593Smuzhiyun #define GCC_USB30_SEC_MASTER_CLK 146 157*4882a593Smuzhiyun #define GCC_USB30_SEC_MASTER_CLK_SRC 147 158*4882a593Smuzhiyun #define GCC_USB30_SEC_MOCK_UTMI_CLK 148 159*4882a593Smuzhiyun #define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 149 160*4882a593Smuzhiyun #define GCC_USB30_SEC_SLEEP_CLK 150 161*4882a593Smuzhiyun #define GCC_USB3_PRIM_CLKREF_CLK 151 162*4882a593Smuzhiyun #define GCC_USB3_PRIM_PHY_AUX_CLK 152 163*4882a593Smuzhiyun #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 153 164*4882a593Smuzhiyun #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 154 165*4882a593Smuzhiyun #define GCC_USB3_PRIM_PHY_PIPE_CLK 155 166*4882a593Smuzhiyun #define GCC_USB3_SEC_CLKREF_CLK 156 167*4882a593Smuzhiyun #define GCC_USB3_SEC_PHY_AUX_CLK 157 168*4882a593Smuzhiyun #define GCC_USB3_SEC_PHY_AUX_CLK_SRC 158 169*4882a593Smuzhiyun #define GCC_USB3_SEC_PHY_PIPE_CLK 159 170*4882a593Smuzhiyun #define GCC_USB3_SEC_PHY_COM_AUX_CLK 160 171*4882a593Smuzhiyun #define GCC_USB_PHY_CFG_AHB2PHY_CLK 161 172*4882a593Smuzhiyun #define GCC_VIDEO_AHB_CLK 162 173*4882a593Smuzhiyun #define GCC_VIDEO_AXI_CLK 163 174*4882a593Smuzhiyun #define GCC_VIDEO_XO_CLK 164 175*4882a593Smuzhiyun #define GPLL0 165 176*4882a593Smuzhiyun #define GPLL0_OUT_EVEN 166 177*4882a593Smuzhiyun #define GPLL0_OUT_MAIN 167 178*4882a593Smuzhiyun #define GCC_GPU_IREF_CLK 168 179*4882a593Smuzhiyun #define GCC_SDCC1_AHB_CLK 169 180*4882a593Smuzhiyun #define GCC_SDCC1_APPS_CLK 170 181*4882a593Smuzhiyun #define GCC_SDCC1_ICE_CORE_CLK 171 182*4882a593Smuzhiyun #define GCC_SDCC1_APPS_CLK_SRC 172 183*4882a593Smuzhiyun #define GCC_SDCC1_ICE_CORE_CLK_SRC 173 184*4882a593Smuzhiyun #define GCC_APC_VS_CLK 174 185*4882a593Smuzhiyun #define GCC_GPU_VS_CLK 175 186*4882a593Smuzhiyun #define GCC_MSS_VS_CLK 176 187*4882a593Smuzhiyun #define GCC_VDDA_VS_CLK 177 188*4882a593Smuzhiyun #define GCC_VDDCX_VS_CLK 178 189*4882a593Smuzhiyun #define GCC_VDDMX_VS_CLK 179 190*4882a593Smuzhiyun #define GCC_VS_CTRL_AHB_CLK 180 191*4882a593Smuzhiyun #define GCC_VS_CTRL_CLK 181 192*4882a593Smuzhiyun #define GCC_VS_CTRL_CLK_SRC 182 193*4882a593Smuzhiyun #define GCC_VSENSOR_CLK_SRC 183 194*4882a593Smuzhiyun #define GPLL4 184 195*4882a593Smuzhiyun #define GCC_CPUSS_DVM_BUS_CLK 185 196*4882a593Smuzhiyun #define GCC_CPUSS_GNOC_CLK 186 197*4882a593Smuzhiyun #define GCC_QSPI_CORE_CLK_SRC 187 198*4882a593Smuzhiyun #define GCC_QSPI_CORE_CLK 188 199*4882a593Smuzhiyun #define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189 200*4882a593Smuzhiyun #define GCC_LPASS_Q6_AXI_CLK 190 201*4882a593Smuzhiyun #define GCC_LPASS_SWAY_CLK 191 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun /* GCC Resets */ 204*4882a593Smuzhiyun #define GCC_MMSS_BCR 0 205*4882a593Smuzhiyun #define GCC_PCIE_0_BCR 1 206*4882a593Smuzhiyun #define GCC_PCIE_1_BCR 2 207*4882a593Smuzhiyun #define GCC_PCIE_PHY_BCR 3 208*4882a593Smuzhiyun #define GCC_PDM_BCR 4 209*4882a593Smuzhiyun #define GCC_PRNG_BCR 5 210*4882a593Smuzhiyun #define GCC_QUPV3_WRAPPER_0_BCR 6 211*4882a593Smuzhiyun #define GCC_QUPV3_WRAPPER_1_BCR 7 212*4882a593Smuzhiyun #define GCC_QUSB2PHY_PRIM_BCR 8 213*4882a593Smuzhiyun #define GCC_QUSB2PHY_SEC_BCR 9 214*4882a593Smuzhiyun #define GCC_SDCC2_BCR 10 215*4882a593Smuzhiyun #define GCC_SDCC4_BCR 11 216*4882a593Smuzhiyun #define GCC_TSIF_BCR 12 217*4882a593Smuzhiyun #define GCC_UFS_CARD_BCR 13 218*4882a593Smuzhiyun #define GCC_UFS_PHY_BCR 14 219*4882a593Smuzhiyun #define GCC_USB30_PRIM_BCR 15 220*4882a593Smuzhiyun #define GCC_USB30_SEC_BCR 16 221*4882a593Smuzhiyun #define GCC_USB3_PHY_PRIM_BCR 17 222*4882a593Smuzhiyun #define GCC_USB3PHY_PHY_PRIM_BCR 18 223*4882a593Smuzhiyun #define GCC_USB3_DP_PHY_PRIM_BCR 19 224*4882a593Smuzhiyun #define GCC_USB3_PHY_SEC_BCR 20 225*4882a593Smuzhiyun #define GCC_USB3PHY_PHY_SEC_BCR 21 226*4882a593Smuzhiyun #define GCC_USB3_DP_PHY_SEC_BCR 22 227*4882a593Smuzhiyun #define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 228*4882a593Smuzhiyun #define GCC_PCIE_0_PHY_BCR 24 229*4882a593Smuzhiyun #define GCC_PCIE_1_PHY_BCR 25 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun /* GCC GDSCRs */ 232*4882a593Smuzhiyun #define PCIE_0_GDSC 0 233*4882a593Smuzhiyun #define PCIE_1_GDSC 1 234*4882a593Smuzhiyun #define UFS_CARD_GDSC 2 235*4882a593Smuzhiyun #define UFS_PHY_GDSC 3 236*4882a593Smuzhiyun #define USB30_PRIM_GDSC 4 237*4882a593Smuzhiyun #define USB30_SEC_GDSC 5 238*4882a593Smuzhiyun #define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 6 239*4882a593Smuzhiyun #define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 7 240*4882a593Smuzhiyun #define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 8 241*4882a593Smuzhiyun #define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 9 242*4882a593Smuzhiyun #define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 10 243*4882a593Smuzhiyun #define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11 244*4882a593Smuzhiyun #define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 12 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun #endif 247