1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* GCC clocks */ 10*4882a593Smuzhiyun #define GCC_GPLL0_MAIN_DIV_CDIV 0 11*4882a593Smuzhiyun #define GPLL0 1 12*4882a593Smuzhiyun #define GPLL0_OUT_EVEN 2 13*4882a593Smuzhiyun #define GPLL1 3 14*4882a593Smuzhiyun #define GPLL4 4 15*4882a593Smuzhiyun #define GPLL6 5 16*4882a593Smuzhiyun #define GPLL7 6 17*4882a593Smuzhiyun #define GCC_AGGRE_UFS_PHY_AXI_CLK 7 18*4882a593Smuzhiyun #define GCC_AGGRE_USB3_PRIM_AXI_CLK 8 19*4882a593Smuzhiyun #define GCC_BOOT_ROM_AHB_CLK 9 20*4882a593Smuzhiyun #define GCC_CAMERA_AHB_CLK 10 21*4882a593Smuzhiyun #define GCC_CAMERA_HF_AXI_CLK 11 22*4882a593Smuzhiyun #define GCC_CAMERA_THROTTLE_HF_AXI_CLK 12 23*4882a593Smuzhiyun #define GCC_CAMERA_XO_CLK 13 24*4882a593Smuzhiyun #define GCC_CE1_AHB_CLK 14 25*4882a593Smuzhiyun #define GCC_CE1_AXI_CLK 15 26*4882a593Smuzhiyun #define GCC_CE1_CLK 16 27*4882a593Smuzhiyun #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17 28*4882a593Smuzhiyun #define GCC_CPUSS_AHB_CLK 18 29*4882a593Smuzhiyun #define GCC_CPUSS_AHB_CLK_SRC 19 30*4882a593Smuzhiyun #define GCC_CPUSS_GNOC_CLK 20 31*4882a593Smuzhiyun #define GCC_CPUSS_RBCPR_CLK 21 32*4882a593Smuzhiyun #define GCC_DDRSS_GPU_AXI_CLK 22 33*4882a593Smuzhiyun #define GCC_DISP_AHB_CLK 23 34*4882a593Smuzhiyun #define GCC_DISP_GPLL0_CLK_SRC 24 35*4882a593Smuzhiyun #define GCC_DISP_GPLL0_DIV_CLK_SRC 25 36*4882a593Smuzhiyun #define GCC_DISP_HF_AXI_CLK 26 37*4882a593Smuzhiyun #define GCC_DISP_THROTTLE_HF_AXI_CLK 27 38*4882a593Smuzhiyun #define GCC_DISP_XO_CLK 28 39*4882a593Smuzhiyun #define GCC_GP1_CLK 29 40*4882a593Smuzhiyun #define GCC_GP1_CLK_SRC 30 41*4882a593Smuzhiyun #define GCC_GP2_CLK 31 42*4882a593Smuzhiyun #define GCC_GP2_CLK_SRC 32 43*4882a593Smuzhiyun #define GCC_GP3_CLK 33 44*4882a593Smuzhiyun #define GCC_GP3_CLK_SRC 34 45*4882a593Smuzhiyun #define GCC_GPU_CFG_AHB_CLK 35 46*4882a593Smuzhiyun #define GCC_GPU_GPLL0_CLK_SRC 36 47*4882a593Smuzhiyun #define GCC_GPU_GPLL0_DIV_CLK_SRC 37 48*4882a593Smuzhiyun #define GCC_GPU_MEMNOC_GFX_CLK 38 49*4882a593Smuzhiyun #define GCC_GPU_SNOC_DVM_GFX_CLK 39 50*4882a593Smuzhiyun #define GCC_NPU_AXI_CLK 40 51*4882a593Smuzhiyun #define GCC_NPU_BWMON_AXI_CLK 41 52*4882a593Smuzhiyun #define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 42 53*4882a593Smuzhiyun #define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 43 54*4882a593Smuzhiyun #define GCC_NPU_CFG_AHB_CLK 44 55*4882a593Smuzhiyun #define GCC_NPU_DMA_CLK 45 56*4882a593Smuzhiyun #define GCC_NPU_GPLL0_CLK_SRC 46 57*4882a593Smuzhiyun #define GCC_NPU_GPLL0_DIV_CLK_SRC 47 58*4882a593Smuzhiyun #define GCC_PDM2_CLK 48 59*4882a593Smuzhiyun #define GCC_PDM2_CLK_SRC 49 60*4882a593Smuzhiyun #define GCC_PDM_AHB_CLK 50 61*4882a593Smuzhiyun #define GCC_PDM_XO4_CLK 51 62*4882a593Smuzhiyun #define GCC_PRNG_AHB_CLK 52 63*4882a593Smuzhiyun #define GCC_QSPI_CNOC_PERIPH_AHB_CLK 53 64*4882a593Smuzhiyun #define GCC_QSPI_CORE_CLK 54 65*4882a593Smuzhiyun #define GCC_QSPI_CORE_CLK_SRC 55 66*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_CORE_2X_CLK 56 67*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_CORE_CLK 57 68*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S0_CLK 58 69*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S0_CLK_SRC 59 70*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S1_CLK 60 71*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S1_CLK_SRC 61 72*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S2_CLK 62 73*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S2_CLK_SRC 63 74*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S3_CLK 64 75*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S3_CLK_SRC 65 76*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S4_CLK 66 77*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S4_CLK_SRC 67 78*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S5_CLK 68 79*4882a593Smuzhiyun #define GCC_QUPV3_WRAP0_S5_CLK_SRC 69 80*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_CORE_2X_CLK 70 81*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_CORE_CLK 71 82*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S0_CLK 72 83*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S0_CLK_SRC 73 84*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S1_CLK 74 85*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S1_CLK_SRC 75 86*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S2_CLK 76 87*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S2_CLK_SRC 77 88*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S3_CLK 78 89*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S3_CLK_SRC 79 90*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S4_CLK 80 91*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S4_CLK_SRC 81 92*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S5_CLK 82 93*4882a593Smuzhiyun #define GCC_QUPV3_WRAP1_S5_CLK_SRC 83 94*4882a593Smuzhiyun #define GCC_QUPV3_WRAP_0_M_AHB_CLK 84 95*4882a593Smuzhiyun #define GCC_QUPV3_WRAP_0_S_AHB_CLK 85 96*4882a593Smuzhiyun #define GCC_QUPV3_WRAP_1_M_AHB_CLK 86 97*4882a593Smuzhiyun #define GCC_QUPV3_WRAP_1_S_AHB_CLK 87 98*4882a593Smuzhiyun #define GCC_SDCC1_AHB_CLK 88 99*4882a593Smuzhiyun #define GCC_SDCC1_APPS_CLK 89 100*4882a593Smuzhiyun #define GCC_SDCC1_APPS_CLK_SRC 90 101*4882a593Smuzhiyun #define GCC_SDCC1_ICE_CORE_CLK 91 102*4882a593Smuzhiyun #define GCC_SDCC1_ICE_CORE_CLK_SRC 92 103*4882a593Smuzhiyun #define GCC_SDCC2_AHB_CLK 93 104*4882a593Smuzhiyun #define GCC_SDCC2_APPS_CLK 94 105*4882a593Smuzhiyun #define GCC_SDCC2_APPS_CLK_SRC 95 106*4882a593Smuzhiyun #define GCC_SYS_NOC_CPUSS_AHB_CLK 96 107*4882a593Smuzhiyun #define GCC_UFS_MEM_CLKREF_CLK 97 108*4882a593Smuzhiyun #define GCC_UFS_PHY_AHB_CLK 98 109*4882a593Smuzhiyun #define GCC_UFS_PHY_AXI_CLK 99 110*4882a593Smuzhiyun #define GCC_UFS_PHY_AXI_CLK_SRC 100 111*4882a593Smuzhiyun #define GCC_UFS_PHY_ICE_CORE_CLK 101 112*4882a593Smuzhiyun #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102 113*4882a593Smuzhiyun #define GCC_UFS_PHY_PHY_AUX_CLK 103 114*4882a593Smuzhiyun #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104 115*4882a593Smuzhiyun #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105 116*4882a593Smuzhiyun #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 106 117*4882a593Smuzhiyun #define GCC_UFS_PHY_UNIPRO_CORE_CLK 107 118*4882a593Smuzhiyun #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 108 119*4882a593Smuzhiyun #define GCC_USB30_PRIM_MASTER_CLK 109 120*4882a593Smuzhiyun #define GCC_USB30_PRIM_MASTER_CLK_SRC 110 121*4882a593Smuzhiyun #define GCC_USB30_PRIM_MOCK_UTMI_CLK 111 122*4882a593Smuzhiyun #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112 123*4882a593Smuzhiyun #define GCC_USB30_PRIM_SLEEP_CLK 113 124*4882a593Smuzhiyun #define GCC_USB3_PRIM_CLKREF_CLK 114 125*4882a593Smuzhiyun #define GCC_USB3_PRIM_PHY_AUX_CLK 115 126*4882a593Smuzhiyun #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116 127*4882a593Smuzhiyun #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117 128*4882a593Smuzhiyun #define GCC_USB3_PRIM_PHY_PIPE_CLK 118 129*4882a593Smuzhiyun #define GCC_USB_PHY_CFG_AHB2PHY_CLK 119 130*4882a593Smuzhiyun #define GCC_VIDEO_AHB_CLK 120 131*4882a593Smuzhiyun #define GCC_VIDEO_AXI_CLK 121 132*4882a593Smuzhiyun #define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122 133*4882a593Smuzhiyun #define GCC_VIDEO_THROTTLE_AXI_CLK 123 134*4882a593Smuzhiyun #define GCC_VIDEO_XO_CLK 124 135*4882a593Smuzhiyun #define GCC_MSS_CFG_AHB_CLK 125 136*4882a593Smuzhiyun #define GCC_MSS_MFAB_AXIS_CLK 126 137*4882a593Smuzhiyun #define GCC_MSS_NAV_AXI_CLK 127 138*4882a593Smuzhiyun #define GCC_MSS_Q6_MEMNOC_AXI_CLK 128 139*4882a593Smuzhiyun #define GCC_MSS_SNOC_AXI_CLK 129 140*4882a593Smuzhiyun #define GCC_SEC_CTRL_CLK_SRC 130 141*4882a593Smuzhiyun #define GCC_LPASS_CFG_NOC_SWAY_CLK 131 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /* GCC resets */ 144*4882a593Smuzhiyun #define GCC_QUSB2PHY_PRIM_BCR 0 145*4882a593Smuzhiyun #define GCC_QUSB2PHY_SEC_BCR 1 146*4882a593Smuzhiyun #define GCC_UFS_PHY_BCR 2 147*4882a593Smuzhiyun #define GCC_USB30_PRIM_BCR 3 148*4882a593Smuzhiyun #define GCC_USB3_DP_PHY_PRIM_BCR 4 149*4882a593Smuzhiyun #define GCC_USB3_DP_PHY_SEC_BCR 5 150*4882a593Smuzhiyun #define GCC_USB3_PHY_PRIM_BCR 6 151*4882a593Smuzhiyun #define GCC_USB3_PHY_SEC_BCR 7 152*4882a593Smuzhiyun #define GCC_USB3PHY_PHY_PRIM_BCR 8 153*4882a593Smuzhiyun #define GCC_USB3PHY_PHY_SEC_BCR 9 154*4882a593Smuzhiyun #define GCC_USB_PHY_CFG_AHB2PHY_BCR 10 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* GCC GDSCRs */ 157*4882a593Smuzhiyun #define UFS_PHY_GDSC 0 158*4882a593Smuzhiyun #define USB30_PRIM_GDSC 1 159*4882a593Smuzhiyun #define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2 160*4882a593Smuzhiyun #define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 3 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun #endif 163