1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define GCC_APSS_AHB_CLK_SRC 0 10*4882a593Smuzhiyun #define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC 1 11*4882a593Smuzhiyun #define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC 2 12*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 3 13*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 4 14*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 5 15*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 6 16*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 7 17*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 8 18*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 9 19*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 10 20*4882a593Smuzhiyun #define GCC_BLSP1_UART0_APPS_CLK_SRC 11 21*4882a593Smuzhiyun #define GCC_BLSP1_UART1_APPS_CLK_SRC 12 22*4882a593Smuzhiyun #define GCC_BLSP1_UART2_APPS_CLK_SRC 13 23*4882a593Smuzhiyun #define GCC_BLSP1_UART3_APPS_CLK_SRC 14 24*4882a593Smuzhiyun #define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC 15 25*4882a593Smuzhiyun #define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC 16 26*4882a593Smuzhiyun #define GCC_BLSP2_UART0_APPS_CLK_SRC 17 27*4882a593Smuzhiyun #define GCC_BYTE0_CLK_SRC 18 28*4882a593Smuzhiyun #define GCC_EMAC_CLK_SRC 19 29*4882a593Smuzhiyun #define GCC_EMAC_PTP_CLK_SRC 20 30*4882a593Smuzhiyun #define GCC_ESC0_CLK_SRC 21 31*4882a593Smuzhiyun #define GCC_APSS_AHB_CLK 22 32*4882a593Smuzhiyun #define GCC_APSS_AXI_CLK 23 33*4882a593Smuzhiyun #define GCC_BIMC_APSS_AXI_CLK 24 34*4882a593Smuzhiyun #define GCC_BIMC_GFX_CLK 25 35*4882a593Smuzhiyun #define GCC_BIMC_MDSS_CLK 26 36*4882a593Smuzhiyun #define GCC_BLSP1_AHB_CLK 27 37*4882a593Smuzhiyun #define GCC_BLSP1_QUP0_I2C_APPS_CLK 28 38*4882a593Smuzhiyun #define GCC_BLSP1_QUP0_SPI_APPS_CLK 29 39*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_I2C_APPS_CLK 30 40*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_SPI_APPS_CLK 31 41*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_I2C_APPS_CLK 32 42*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_SPI_APPS_CLK 33 43*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_I2C_APPS_CLK 34 44*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_SPI_APPS_CLK 35 45*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_I2C_APPS_CLK 36 46*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_SPI_APPS_CLK 37 47*4882a593Smuzhiyun #define GCC_BLSP1_UART0_APPS_CLK 38 48*4882a593Smuzhiyun #define GCC_BLSP1_UART1_APPS_CLK 39 49*4882a593Smuzhiyun #define GCC_BLSP1_UART2_APPS_CLK 40 50*4882a593Smuzhiyun #define GCC_BLSP1_UART3_APPS_CLK 41 51*4882a593Smuzhiyun #define GCC_BLSP2_AHB_CLK 42 52*4882a593Smuzhiyun #define GCC_BLSP2_QUP0_I2C_APPS_CLK 43 53*4882a593Smuzhiyun #define GCC_BLSP2_QUP0_SPI_APPS_CLK 44 54*4882a593Smuzhiyun #define GCC_BLSP2_UART0_APPS_CLK 45 55*4882a593Smuzhiyun #define GCC_BOOT_ROM_AHB_CLK 46 56*4882a593Smuzhiyun #define GCC_DCC_CLK 47 57*4882a593Smuzhiyun #define GCC_GENI_IR_H_CLK 48 58*4882a593Smuzhiyun #define GCC_ETH_AXI_CLK 49 59*4882a593Smuzhiyun #define GCC_ETH_PTP_CLK 50 60*4882a593Smuzhiyun #define GCC_ETH_RGMII_CLK 51 61*4882a593Smuzhiyun #define GCC_ETH_SLAVE_AHB_CLK 52 62*4882a593Smuzhiyun #define GCC_GENI_IR_S_CLK 53 63*4882a593Smuzhiyun #define GCC_GP1_CLK 54 64*4882a593Smuzhiyun #define GCC_GP2_CLK 55 65*4882a593Smuzhiyun #define GCC_GP3_CLK 56 66*4882a593Smuzhiyun #define GCC_MDSS_AHB_CLK 57 67*4882a593Smuzhiyun #define GCC_MDSS_AXI_CLK 58 68*4882a593Smuzhiyun #define GCC_MDSS_BYTE0_CLK 59 69*4882a593Smuzhiyun #define GCC_MDSS_ESC0_CLK 60 70*4882a593Smuzhiyun #define GCC_MDSS_HDMI_APP_CLK 61 71*4882a593Smuzhiyun #define GCC_MDSS_HDMI_PCLK_CLK 62 72*4882a593Smuzhiyun #define GCC_MDSS_MDP_CLK 63 73*4882a593Smuzhiyun #define GCC_MDSS_PCLK0_CLK 64 74*4882a593Smuzhiyun #define GCC_MDSS_VSYNC_CLK 65 75*4882a593Smuzhiyun #define GCC_OXILI_AHB_CLK 66 76*4882a593Smuzhiyun #define GCC_OXILI_GFX3D_CLK 67 77*4882a593Smuzhiyun #define GCC_PCIE_0_AUX_CLK 68 78*4882a593Smuzhiyun #define GCC_PCIE_0_CFG_AHB_CLK 69 79*4882a593Smuzhiyun #define GCC_PCIE_0_MSTR_AXI_CLK 70 80*4882a593Smuzhiyun #define GCC_PCIE_0_PIPE_CLK 71 81*4882a593Smuzhiyun #define GCC_PCIE_0_SLV_AXI_CLK 72 82*4882a593Smuzhiyun #define GCC_PCNOC_USB2_CLK 73 83*4882a593Smuzhiyun #define GCC_PCNOC_USB3_CLK 74 84*4882a593Smuzhiyun #define GCC_PDM2_CLK 75 85*4882a593Smuzhiyun #define GCC_PDM_AHB_CLK 76 86*4882a593Smuzhiyun #define GCC_VSYNC_CLK_SRC 77 87*4882a593Smuzhiyun #define GCC_PRNG_AHB_CLK 78 88*4882a593Smuzhiyun #define GCC_PWM0_XO512_CLK 79 89*4882a593Smuzhiyun #define GCC_PWM1_XO512_CLK 80 90*4882a593Smuzhiyun #define GCC_PWM2_XO512_CLK 81 91*4882a593Smuzhiyun #define GCC_SDCC1_AHB_CLK 82 92*4882a593Smuzhiyun #define GCC_SDCC1_APPS_CLK 83 93*4882a593Smuzhiyun #define GCC_SDCC1_ICE_CORE_CLK 84 94*4882a593Smuzhiyun #define GCC_SDCC2_AHB_CLK 85 95*4882a593Smuzhiyun #define GCC_SDCC2_APPS_CLK 86 96*4882a593Smuzhiyun #define GCC_SYS_NOC_USB3_CLK 87 97*4882a593Smuzhiyun #define GCC_USB20_MOCK_UTMI_CLK 88 98*4882a593Smuzhiyun #define GCC_USB2A_PHY_SLEEP_CLK 89 99*4882a593Smuzhiyun #define GCC_USB30_MASTER_CLK 90 100*4882a593Smuzhiyun #define GCC_USB30_MOCK_UTMI_CLK 91 101*4882a593Smuzhiyun #define GCC_USB30_SLEEP_CLK 92 102*4882a593Smuzhiyun #define GCC_USB3_PHY_AUX_CLK 93 103*4882a593Smuzhiyun #define GCC_USB3_PHY_PIPE_CLK 94 104*4882a593Smuzhiyun #define GCC_USB_HS_PHY_CFG_AHB_CLK 95 105*4882a593Smuzhiyun #define GCC_USB_HS_SYSTEM_CLK 96 106*4882a593Smuzhiyun #define GCC_GFX3D_CLK_SRC 97 107*4882a593Smuzhiyun #define GCC_GP1_CLK_SRC 98 108*4882a593Smuzhiyun #define GCC_GP2_CLK_SRC 99 109*4882a593Smuzhiyun #define GCC_GP3_CLK_SRC 100 110*4882a593Smuzhiyun #define GCC_GPLL0_OUT_MAIN 101 111*4882a593Smuzhiyun #define GCC_GPLL1_OUT_MAIN 102 112*4882a593Smuzhiyun #define GCC_GPLL3_OUT_MAIN 103 113*4882a593Smuzhiyun #define GCC_GPLL4_OUT_MAIN 104 114*4882a593Smuzhiyun #define GCC_HDMI_APP_CLK_SRC 105 115*4882a593Smuzhiyun #define GCC_HDMI_PCLK_CLK_SRC 106 116*4882a593Smuzhiyun #define GCC_MDP_CLK_SRC 107 117*4882a593Smuzhiyun #define GCC_PCIE_0_AUX_CLK_SRC 108 118*4882a593Smuzhiyun #define GCC_PCIE_0_PIPE_CLK_SRC 109 119*4882a593Smuzhiyun #define GCC_PCLK0_CLK_SRC 110 120*4882a593Smuzhiyun #define GCC_PDM2_CLK_SRC 111 121*4882a593Smuzhiyun #define GCC_SDCC1_APPS_CLK_SRC 112 122*4882a593Smuzhiyun #define GCC_SDCC1_ICE_CORE_CLK_SRC 113 123*4882a593Smuzhiyun #define GCC_SDCC2_APPS_CLK_SRC 114 124*4882a593Smuzhiyun #define GCC_USB20_MOCK_UTMI_CLK_SRC 115 125*4882a593Smuzhiyun #define GCC_USB30_MASTER_CLK_SRC 116 126*4882a593Smuzhiyun #define GCC_USB30_MOCK_UTMI_CLK_SRC 117 127*4882a593Smuzhiyun #define GCC_USB3_PHY_AUX_CLK_SRC 118 128*4882a593Smuzhiyun #define GCC_USB_HS_SYSTEM_CLK_SRC 119 129*4882a593Smuzhiyun #define GCC_GPLL0_AO_CLK_SRC 120 130*4882a593Smuzhiyun #define GCC_USB_HS_INACTIVITY_TIMERS_CLK 122 131*4882a593Smuzhiyun #define GCC_GPLL0_AO_OUT_MAIN 123 132*4882a593Smuzhiyun #define GCC_GPLL0_SLEEP_CLK_SRC 124 133*4882a593Smuzhiyun #define GCC_GPLL6 125 134*4882a593Smuzhiyun #define GCC_GPLL6_OUT_AUX 126 135*4882a593Smuzhiyun #define GCC_MDSS_MDP_VOTE_CLK 127 136*4882a593Smuzhiyun #define GCC_MDSS_ROTATOR_VOTE_CLK 128 137*4882a593Smuzhiyun #define GCC_BIMC_GPU_CLK 129 138*4882a593Smuzhiyun #define GCC_GTCU_AHB_CLK 130 139*4882a593Smuzhiyun #define GCC_GFX_TCU_CLK 131 140*4882a593Smuzhiyun #define GCC_GFX_TBU_CLK 132 141*4882a593Smuzhiyun #define GCC_SMMU_CFG_CLK 133 142*4882a593Smuzhiyun #define GCC_APSS_TCU_CLK 134 143*4882a593Smuzhiyun #define GCC_CRYPTO_AHB_CLK 135 144*4882a593Smuzhiyun #define GCC_CRYPTO_AXI_CLK 136 145*4882a593Smuzhiyun #define GCC_CRYPTO_CLK 137 146*4882a593Smuzhiyun #define GCC_MDP_TBU_CLK 138 147*4882a593Smuzhiyun #define GCC_QDSS_DAP_CLK 139 148*4882a593Smuzhiyun #define GCC_DCC_XO_CLK 140 149*4882a593Smuzhiyun #define GCC_WCSS_Q6_AHB_CLK 141 150*4882a593Smuzhiyun #define GCC_WCSS_Q6_AXIM_CLK 142 151*4882a593Smuzhiyun #define GCC_CDSP_CFG_AHB_CLK 143 152*4882a593Smuzhiyun #define GCC_BIMC_CDSP_CLK 144 153*4882a593Smuzhiyun #define GCC_CDSP_TBU_CLK 145 154*4882a593Smuzhiyun #define GCC_CDSP_BIMC_CLK_SRC 146 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #define GCC_GENI_IR_BCR 0 157*4882a593Smuzhiyun #define GCC_USB_HS_BCR 1 158*4882a593Smuzhiyun #define GCC_USB2_HS_PHY_ONLY_BCR 2 159*4882a593Smuzhiyun #define GCC_QUSB2_PHY_BCR 3 160*4882a593Smuzhiyun #define GCC_USB_HS_PHY_CFG_AHB_BCR 4 161*4882a593Smuzhiyun #define GCC_USB2A_PHY_BCR 5 162*4882a593Smuzhiyun #define GCC_USB3_PHY_BCR 6 163*4882a593Smuzhiyun #define GCC_USB_30_BCR 7 164*4882a593Smuzhiyun #define GCC_USB3PHY_PHY_BCR 8 165*4882a593Smuzhiyun #define GCC_PCIE_0_BCR 9 166*4882a593Smuzhiyun #define GCC_PCIE_0_PHY_BCR 10 167*4882a593Smuzhiyun #define GCC_PCIE_0_LINK_DOWN_BCR 11 168*4882a593Smuzhiyun #define GCC_PCIEPHY_0_PHY_BCR 12 169*4882a593Smuzhiyun #define GCC_EMAC_BCR 13 170*4882a593Smuzhiyun #define GCC_CDSP_RESTART 14 171*4882a593Smuzhiyun #define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 15 172*4882a593Smuzhiyun #define GCC_PCIE_0_AHB_ARES 16 173*4882a593Smuzhiyun #define GCC_PCIE_0_AXI_SLAVE_ARES 17 174*4882a593Smuzhiyun #define GCC_PCIE_0_AXI_MASTER_ARES 18 175*4882a593Smuzhiyun #define GCC_PCIE_0_CORE_STICKY_ARES 19 176*4882a593Smuzhiyun #define GCC_PCIE_0_SLEEP_ARES 20 177*4882a593Smuzhiyun #define GCC_PCIE_0_PIPE_ARES 21 178*4882a593Smuzhiyun #define GCC_WDSP_RESTART 22 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun #endif 181