1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define GPLL0 0 10*4882a593Smuzhiyun #define GPLL0_MAIN 1 11*4882a593Smuzhiyun #define GCC_SLEEP_CLK_SRC 2 12*4882a593Smuzhiyun #define BLSP1_QUP1_I2C_APPS_CLK_SRC 3 13*4882a593Smuzhiyun #define BLSP1_QUP1_SPI_APPS_CLK_SRC 4 14*4882a593Smuzhiyun #define BLSP1_QUP2_I2C_APPS_CLK_SRC 5 15*4882a593Smuzhiyun #define BLSP1_QUP2_SPI_APPS_CLK_SRC 6 16*4882a593Smuzhiyun #define BLSP1_QUP3_I2C_APPS_CLK_SRC 7 17*4882a593Smuzhiyun #define BLSP1_QUP3_SPI_APPS_CLK_SRC 8 18*4882a593Smuzhiyun #define BLSP1_QUP4_I2C_APPS_CLK_SRC 9 19*4882a593Smuzhiyun #define BLSP1_QUP4_SPI_APPS_CLK_SRC 10 20*4882a593Smuzhiyun #define BLSP1_QUP5_I2C_APPS_CLK_SRC 11 21*4882a593Smuzhiyun #define BLSP1_QUP5_SPI_APPS_CLK_SRC 12 22*4882a593Smuzhiyun #define BLSP1_QUP6_I2C_APPS_CLK_SRC 13 23*4882a593Smuzhiyun #define BLSP1_QUP6_SPI_APPS_CLK_SRC 14 24*4882a593Smuzhiyun #define BLSP1_UART1_APPS_CLK_SRC 15 25*4882a593Smuzhiyun #define BLSP1_UART2_APPS_CLK_SRC 16 26*4882a593Smuzhiyun #define BLSP1_UART3_APPS_CLK_SRC 17 27*4882a593Smuzhiyun #define BLSP1_UART4_APPS_CLK_SRC 18 28*4882a593Smuzhiyun #define BLSP1_UART5_APPS_CLK_SRC 19 29*4882a593Smuzhiyun #define BLSP1_UART6_APPS_CLK_SRC 20 30*4882a593Smuzhiyun #define GCC_BLSP1_AHB_CLK 21 31*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_I2C_APPS_CLK 22 32*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_SPI_APPS_CLK 23 33*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_I2C_APPS_CLK 24 34*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_SPI_APPS_CLK 25 35*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_I2C_APPS_CLK 26 36*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_SPI_APPS_CLK 27 37*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_I2C_APPS_CLK 28 38*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_SPI_APPS_CLK 29 39*4882a593Smuzhiyun #define GCC_BLSP1_QUP5_I2C_APPS_CLK 30 40*4882a593Smuzhiyun #define GCC_BLSP1_QUP5_SPI_APPS_CLK 31 41*4882a593Smuzhiyun #define GCC_BLSP1_QUP6_I2C_APPS_CLK 32 42*4882a593Smuzhiyun #define GCC_BLSP1_QUP6_SPI_APPS_CLK 33 43*4882a593Smuzhiyun #define GCC_BLSP1_UART1_APPS_CLK 34 44*4882a593Smuzhiyun #define GCC_BLSP1_UART2_APPS_CLK 35 45*4882a593Smuzhiyun #define GCC_BLSP1_UART3_APPS_CLK 36 46*4882a593Smuzhiyun #define GCC_BLSP1_UART4_APPS_CLK 37 47*4882a593Smuzhiyun #define GCC_BLSP1_UART5_APPS_CLK 38 48*4882a593Smuzhiyun #define GCC_BLSP1_UART6_APPS_CLK 39 49*4882a593Smuzhiyun #define GCC_PRNG_AHB_CLK 40 50*4882a593Smuzhiyun #define GCC_QPIC_AHB_CLK 41 51*4882a593Smuzhiyun #define GCC_QPIC_CLK 42 52*4882a593Smuzhiyun #define PCNOC_BFDCD_CLK_SRC 43 53*4882a593Smuzhiyun #define GPLL2_MAIN 44 54*4882a593Smuzhiyun #define GPLL2 45 55*4882a593Smuzhiyun #define GPLL4_MAIN 46 56*4882a593Smuzhiyun #define GPLL4 47 57*4882a593Smuzhiyun #define GPLL6_MAIN 48 58*4882a593Smuzhiyun #define GPLL6 49 59*4882a593Smuzhiyun #define UBI32_PLL_MAIN 50 60*4882a593Smuzhiyun #define UBI32_PLL 51 61*4882a593Smuzhiyun #define NSS_CRYPTO_PLL_MAIN 52 62*4882a593Smuzhiyun #define NSS_CRYPTO_PLL 53 63*4882a593Smuzhiyun #define PCIE0_AXI_CLK_SRC 54 64*4882a593Smuzhiyun #define PCIE0_AUX_CLK_SRC 55 65*4882a593Smuzhiyun #define PCIE0_PIPE_CLK_SRC 56 66*4882a593Smuzhiyun #define PCIE1_AXI_CLK_SRC 57 67*4882a593Smuzhiyun #define PCIE1_AUX_CLK_SRC 58 68*4882a593Smuzhiyun #define PCIE1_PIPE_CLK_SRC 59 69*4882a593Smuzhiyun #define SDCC1_APPS_CLK_SRC 60 70*4882a593Smuzhiyun #define SDCC1_ICE_CORE_CLK_SRC 61 71*4882a593Smuzhiyun #define SDCC2_APPS_CLK_SRC 62 72*4882a593Smuzhiyun #define USB0_MASTER_CLK_SRC 63 73*4882a593Smuzhiyun #define USB0_AUX_CLK_SRC 64 74*4882a593Smuzhiyun #define USB0_MOCK_UTMI_CLK_SRC 65 75*4882a593Smuzhiyun #define USB0_PIPE_CLK_SRC 66 76*4882a593Smuzhiyun #define USB1_MASTER_CLK_SRC 67 77*4882a593Smuzhiyun #define USB1_AUX_CLK_SRC 68 78*4882a593Smuzhiyun #define USB1_MOCK_UTMI_CLK_SRC 69 79*4882a593Smuzhiyun #define USB1_PIPE_CLK_SRC 70 80*4882a593Smuzhiyun #define GCC_XO_CLK_SRC 71 81*4882a593Smuzhiyun #define SYSTEM_NOC_BFDCD_CLK_SRC 72 82*4882a593Smuzhiyun #define NSS_CE_CLK_SRC 73 83*4882a593Smuzhiyun #define NSS_NOC_BFDCD_CLK_SRC 74 84*4882a593Smuzhiyun #define NSS_CRYPTO_CLK_SRC 75 85*4882a593Smuzhiyun #define NSS_UBI0_CLK_SRC 76 86*4882a593Smuzhiyun #define NSS_UBI0_DIV_CLK_SRC 77 87*4882a593Smuzhiyun #define NSS_UBI1_CLK_SRC 78 88*4882a593Smuzhiyun #define NSS_UBI1_DIV_CLK_SRC 79 89*4882a593Smuzhiyun #define UBI_MPT_CLK_SRC 80 90*4882a593Smuzhiyun #define NSS_IMEM_CLK_SRC 81 91*4882a593Smuzhiyun #define NSS_PPE_CLK_SRC 82 92*4882a593Smuzhiyun #define NSS_PORT1_RX_CLK_SRC 83 93*4882a593Smuzhiyun #define NSS_PORT1_RX_DIV_CLK_SRC 84 94*4882a593Smuzhiyun #define NSS_PORT1_TX_CLK_SRC 85 95*4882a593Smuzhiyun #define NSS_PORT1_TX_DIV_CLK_SRC 86 96*4882a593Smuzhiyun #define NSS_PORT2_RX_CLK_SRC 87 97*4882a593Smuzhiyun #define NSS_PORT2_RX_DIV_CLK_SRC 88 98*4882a593Smuzhiyun #define NSS_PORT2_TX_CLK_SRC 89 99*4882a593Smuzhiyun #define NSS_PORT2_TX_DIV_CLK_SRC 90 100*4882a593Smuzhiyun #define NSS_PORT3_RX_CLK_SRC 91 101*4882a593Smuzhiyun #define NSS_PORT3_RX_DIV_CLK_SRC 92 102*4882a593Smuzhiyun #define NSS_PORT3_TX_CLK_SRC 93 103*4882a593Smuzhiyun #define NSS_PORT3_TX_DIV_CLK_SRC 94 104*4882a593Smuzhiyun #define NSS_PORT4_RX_CLK_SRC 95 105*4882a593Smuzhiyun #define NSS_PORT4_RX_DIV_CLK_SRC 96 106*4882a593Smuzhiyun #define NSS_PORT4_TX_CLK_SRC 97 107*4882a593Smuzhiyun #define NSS_PORT4_TX_DIV_CLK_SRC 98 108*4882a593Smuzhiyun #define NSS_PORT5_RX_CLK_SRC 99 109*4882a593Smuzhiyun #define NSS_PORT5_RX_DIV_CLK_SRC 100 110*4882a593Smuzhiyun #define NSS_PORT5_TX_CLK_SRC 101 111*4882a593Smuzhiyun #define NSS_PORT5_TX_DIV_CLK_SRC 102 112*4882a593Smuzhiyun #define NSS_PORT6_RX_CLK_SRC 103 113*4882a593Smuzhiyun #define NSS_PORT6_RX_DIV_CLK_SRC 104 114*4882a593Smuzhiyun #define NSS_PORT6_TX_CLK_SRC 105 115*4882a593Smuzhiyun #define NSS_PORT6_TX_DIV_CLK_SRC 106 116*4882a593Smuzhiyun #define CRYPTO_CLK_SRC 107 117*4882a593Smuzhiyun #define GP1_CLK_SRC 108 118*4882a593Smuzhiyun #define GP2_CLK_SRC 109 119*4882a593Smuzhiyun #define GP3_CLK_SRC 110 120*4882a593Smuzhiyun #define GCC_PCIE0_AHB_CLK 111 121*4882a593Smuzhiyun #define GCC_PCIE0_AUX_CLK 112 122*4882a593Smuzhiyun #define GCC_PCIE0_AXI_M_CLK 113 123*4882a593Smuzhiyun #define GCC_PCIE0_AXI_S_CLK 114 124*4882a593Smuzhiyun #define GCC_PCIE0_PIPE_CLK 115 125*4882a593Smuzhiyun #define GCC_SYS_NOC_PCIE0_AXI_CLK 116 126*4882a593Smuzhiyun #define GCC_PCIE1_AHB_CLK 117 127*4882a593Smuzhiyun #define GCC_PCIE1_AUX_CLK 118 128*4882a593Smuzhiyun #define GCC_PCIE1_AXI_M_CLK 119 129*4882a593Smuzhiyun #define GCC_PCIE1_AXI_S_CLK 120 130*4882a593Smuzhiyun #define GCC_PCIE1_PIPE_CLK 121 131*4882a593Smuzhiyun #define GCC_SYS_NOC_PCIE1_AXI_CLK 122 132*4882a593Smuzhiyun #define GCC_USB0_AUX_CLK 123 133*4882a593Smuzhiyun #define GCC_SYS_NOC_USB0_AXI_CLK 124 134*4882a593Smuzhiyun #define GCC_USB0_MASTER_CLK 125 135*4882a593Smuzhiyun #define GCC_USB0_MOCK_UTMI_CLK 126 136*4882a593Smuzhiyun #define GCC_USB0_PHY_CFG_AHB_CLK 127 137*4882a593Smuzhiyun #define GCC_USB0_PIPE_CLK 128 138*4882a593Smuzhiyun #define GCC_USB0_SLEEP_CLK 129 139*4882a593Smuzhiyun #define GCC_USB1_AUX_CLK 130 140*4882a593Smuzhiyun #define GCC_SYS_NOC_USB1_AXI_CLK 131 141*4882a593Smuzhiyun #define GCC_USB1_MASTER_CLK 132 142*4882a593Smuzhiyun #define GCC_USB1_MOCK_UTMI_CLK 133 143*4882a593Smuzhiyun #define GCC_USB1_PHY_CFG_AHB_CLK 134 144*4882a593Smuzhiyun #define GCC_USB1_PIPE_CLK 135 145*4882a593Smuzhiyun #define GCC_USB1_SLEEP_CLK 136 146*4882a593Smuzhiyun #define GCC_SDCC1_AHB_CLK 137 147*4882a593Smuzhiyun #define GCC_SDCC1_APPS_CLK 138 148*4882a593Smuzhiyun #define GCC_SDCC1_ICE_CORE_CLK 139 149*4882a593Smuzhiyun #define GCC_SDCC2_AHB_CLK 140 150*4882a593Smuzhiyun #define GCC_SDCC2_APPS_CLK 141 151*4882a593Smuzhiyun #define GCC_MEM_NOC_NSS_AXI_CLK 142 152*4882a593Smuzhiyun #define GCC_NSS_CE_APB_CLK 143 153*4882a593Smuzhiyun #define GCC_NSS_CE_AXI_CLK 144 154*4882a593Smuzhiyun #define GCC_NSS_CFG_CLK 145 155*4882a593Smuzhiyun #define GCC_NSS_CRYPTO_CLK 146 156*4882a593Smuzhiyun #define GCC_NSS_CSR_CLK 147 157*4882a593Smuzhiyun #define GCC_NSS_EDMA_CFG_CLK 148 158*4882a593Smuzhiyun #define GCC_NSS_EDMA_CLK 149 159*4882a593Smuzhiyun #define GCC_NSS_IMEM_CLK 150 160*4882a593Smuzhiyun #define GCC_NSS_NOC_CLK 151 161*4882a593Smuzhiyun #define GCC_NSS_PPE_BTQ_CLK 152 162*4882a593Smuzhiyun #define GCC_NSS_PPE_CFG_CLK 153 163*4882a593Smuzhiyun #define GCC_NSS_PPE_CLK 154 164*4882a593Smuzhiyun #define GCC_NSS_PPE_IPE_CLK 155 165*4882a593Smuzhiyun #define GCC_NSS_PTP_REF_CLK 156 166*4882a593Smuzhiyun #define GCC_NSSNOC_CE_APB_CLK 157 167*4882a593Smuzhiyun #define GCC_NSSNOC_CE_AXI_CLK 158 168*4882a593Smuzhiyun #define GCC_NSSNOC_CRYPTO_CLK 159 169*4882a593Smuzhiyun #define GCC_NSSNOC_PPE_CFG_CLK 160 170*4882a593Smuzhiyun #define GCC_NSSNOC_PPE_CLK 161 171*4882a593Smuzhiyun #define GCC_NSSNOC_QOSGEN_REF_CLK 162 172*4882a593Smuzhiyun #define GCC_NSSNOC_SNOC_CLK 163 173*4882a593Smuzhiyun #define GCC_NSSNOC_TIMEOUT_REF_CLK 164 174*4882a593Smuzhiyun #define GCC_NSSNOC_UBI0_AHB_CLK 165 175*4882a593Smuzhiyun #define GCC_NSSNOC_UBI1_AHB_CLK 166 176*4882a593Smuzhiyun #define GCC_UBI0_AHB_CLK 167 177*4882a593Smuzhiyun #define GCC_UBI0_AXI_CLK 168 178*4882a593Smuzhiyun #define GCC_UBI0_NC_AXI_CLK 169 179*4882a593Smuzhiyun #define GCC_UBI0_CORE_CLK 170 180*4882a593Smuzhiyun #define GCC_UBI0_MPT_CLK 171 181*4882a593Smuzhiyun #define GCC_UBI1_AHB_CLK 172 182*4882a593Smuzhiyun #define GCC_UBI1_AXI_CLK 173 183*4882a593Smuzhiyun #define GCC_UBI1_NC_AXI_CLK 174 184*4882a593Smuzhiyun #define GCC_UBI1_CORE_CLK 175 185*4882a593Smuzhiyun #define GCC_UBI1_MPT_CLK 176 186*4882a593Smuzhiyun #define GCC_CMN_12GPLL_AHB_CLK 177 187*4882a593Smuzhiyun #define GCC_CMN_12GPLL_SYS_CLK 178 188*4882a593Smuzhiyun #define GCC_MDIO_AHB_CLK 179 189*4882a593Smuzhiyun #define GCC_UNIPHY0_AHB_CLK 180 190*4882a593Smuzhiyun #define GCC_UNIPHY0_SYS_CLK 181 191*4882a593Smuzhiyun #define GCC_UNIPHY1_AHB_CLK 182 192*4882a593Smuzhiyun #define GCC_UNIPHY1_SYS_CLK 183 193*4882a593Smuzhiyun #define GCC_UNIPHY2_AHB_CLK 184 194*4882a593Smuzhiyun #define GCC_UNIPHY2_SYS_CLK 185 195*4882a593Smuzhiyun #define GCC_NSS_PORT1_RX_CLK 186 196*4882a593Smuzhiyun #define GCC_NSS_PORT1_TX_CLK 187 197*4882a593Smuzhiyun #define GCC_NSS_PORT2_RX_CLK 188 198*4882a593Smuzhiyun #define GCC_NSS_PORT2_TX_CLK 189 199*4882a593Smuzhiyun #define GCC_NSS_PORT3_RX_CLK 190 200*4882a593Smuzhiyun #define GCC_NSS_PORT3_TX_CLK 191 201*4882a593Smuzhiyun #define GCC_NSS_PORT4_RX_CLK 192 202*4882a593Smuzhiyun #define GCC_NSS_PORT4_TX_CLK 193 203*4882a593Smuzhiyun #define GCC_NSS_PORT5_RX_CLK 194 204*4882a593Smuzhiyun #define GCC_NSS_PORT5_TX_CLK 195 205*4882a593Smuzhiyun #define GCC_NSS_PORT6_RX_CLK 196 206*4882a593Smuzhiyun #define GCC_NSS_PORT6_TX_CLK 197 207*4882a593Smuzhiyun #define GCC_PORT1_MAC_CLK 198 208*4882a593Smuzhiyun #define GCC_PORT2_MAC_CLK 199 209*4882a593Smuzhiyun #define GCC_PORT3_MAC_CLK 200 210*4882a593Smuzhiyun #define GCC_PORT4_MAC_CLK 201 211*4882a593Smuzhiyun #define GCC_PORT5_MAC_CLK 202 212*4882a593Smuzhiyun #define GCC_PORT6_MAC_CLK 203 213*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT1_RX_CLK 204 214*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT1_TX_CLK 205 215*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT2_RX_CLK 206 216*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT2_TX_CLK 207 217*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT3_RX_CLK 208 218*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT3_TX_CLK 209 219*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT4_RX_CLK 210 220*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT4_TX_CLK 211 221*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT5_RX_CLK 212 222*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT5_TX_CLK 213 223*4882a593Smuzhiyun #define GCC_UNIPHY1_PORT5_RX_CLK 214 224*4882a593Smuzhiyun #define GCC_UNIPHY1_PORT5_TX_CLK 215 225*4882a593Smuzhiyun #define GCC_UNIPHY2_PORT6_RX_CLK 216 226*4882a593Smuzhiyun #define GCC_UNIPHY2_PORT6_TX_CLK 217 227*4882a593Smuzhiyun #define GCC_CRYPTO_AHB_CLK 218 228*4882a593Smuzhiyun #define GCC_CRYPTO_AXI_CLK 219 229*4882a593Smuzhiyun #define GCC_CRYPTO_CLK 220 230*4882a593Smuzhiyun #define GCC_GP1_CLK 221 231*4882a593Smuzhiyun #define GCC_GP2_CLK 222 232*4882a593Smuzhiyun #define GCC_GP3_CLK 223 233*4882a593Smuzhiyun #define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 234*4882a593Smuzhiyun #define GCC_PCIE0_RCHNG_CLK_SRC 225 235*4882a593Smuzhiyun #define GCC_PCIE0_RCHNG_CLK 226 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun #define GCC_BLSP1_BCR 0 238*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_BCR 1 239*4882a593Smuzhiyun #define GCC_BLSP1_UART1_BCR 2 240*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_BCR 3 241*4882a593Smuzhiyun #define GCC_BLSP1_UART2_BCR 4 242*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_BCR 5 243*4882a593Smuzhiyun #define GCC_BLSP1_UART3_BCR 6 244*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_BCR 7 245*4882a593Smuzhiyun #define GCC_BLSP1_UART4_BCR 8 246*4882a593Smuzhiyun #define GCC_BLSP1_QUP5_BCR 9 247*4882a593Smuzhiyun #define GCC_BLSP1_UART5_BCR 10 248*4882a593Smuzhiyun #define GCC_BLSP1_QUP6_BCR 11 249*4882a593Smuzhiyun #define GCC_BLSP1_UART6_BCR 12 250*4882a593Smuzhiyun #define GCC_IMEM_BCR 13 251*4882a593Smuzhiyun #define GCC_SMMU_BCR 14 252*4882a593Smuzhiyun #define GCC_APSS_TCU_BCR 15 253*4882a593Smuzhiyun #define GCC_SMMU_XPU_BCR 16 254*4882a593Smuzhiyun #define GCC_PCNOC_TBU_BCR 17 255*4882a593Smuzhiyun #define GCC_SMMU_CFG_BCR 18 256*4882a593Smuzhiyun #define GCC_PRNG_BCR 19 257*4882a593Smuzhiyun #define GCC_BOOT_ROM_BCR 20 258*4882a593Smuzhiyun #define GCC_CRYPTO_BCR 21 259*4882a593Smuzhiyun #define GCC_WCSS_BCR 22 260*4882a593Smuzhiyun #define GCC_WCSS_Q6_BCR 23 261*4882a593Smuzhiyun #define GCC_NSS_BCR 24 262*4882a593Smuzhiyun #define GCC_SEC_CTRL_BCR 25 263*4882a593Smuzhiyun #define GCC_ADSS_BCR 26 264*4882a593Smuzhiyun #define GCC_DDRSS_BCR 27 265*4882a593Smuzhiyun #define GCC_SYSTEM_NOC_BCR 28 266*4882a593Smuzhiyun #define GCC_PCNOC_BCR 29 267*4882a593Smuzhiyun #define GCC_TCSR_BCR 30 268*4882a593Smuzhiyun #define GCC_QDSS_BCR 31 269*4882a593Smuzhiyun #define GCC_DCD_BCR 32 270*4882a593Smuzhiyun #define GCC_MSG_RAM_BCR 33 271*4882a593Smuzhiyun #define GCC_MPM_BCR 34 272*4882a593Smuzhiyun #define GCC_SPMI_BCR 35 273*4882a593Smuzhiyun #define GCC_SPDM_BCR 36 274*4882a593Smuzhiyun #define GCC_RBCPR_BCR 37 275*4882a593Smuzhiyun #define GCC_RBCPR_MX_BCR 38 276*4882a593Smuzhiyun #define GCC_TLMM_BCR 39 277*4882a593Smuzhiyun #define GCC_RBCPR_WCSS_BCR 40 278*4882a593Smuzhiyun #define GCC_USB0_PHY_BCR 41 279*4882a593Smuzhiyun #define GCC_USB3PHY_0_PHY_BCR 42 280*4882a593Smuzhiyun #define GCC_USB0_BCR 43 281*4882a593Smuzhiyun #define GCC_USB1_PHY_BCR 44 282*4882a593Smuzhiyun #define GCC_USB3PHY_1_PHY_BCR 45 283*4882a593Smuzhiyun #define GCC_USB1_BCR 46 284*4882a593Smuzhiyun #define GCC_QUSB2_0_PHY_BCR 47 285*4882a593Smuzhiyun #define GCC_QUSB2_1_PHY_BCR 48 286*4882a593Smuzhiyun #define GCC_SDCC1_BCR 49 287*4882a593Smuzhiyun #define GCC_SDCC2_BCR 50 288*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT0_BCR 51 289*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT2_BCR 52 290*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT3_BCR 53 291*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT0_BCR 54 292*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT1_BCR 55 293*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT2_BCR 56 294*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT3_BCR 57 295*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT4_BCR 58 296*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT5_BCR 59 297*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT6_BCR 60 298*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT7_BCR 61 299*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT8_BCR 62 300*4882a593Smuzhiyun #define GCC_PCNOC_BUS_TIMEOUT9_BCR 63 301*4882a593Smuzhiyun #define GCC_UNIPHY0_BCR 64 302*4882a593Smuzhiyun #define GCC_UNIPHY1_BCR 65 303*4882a593Smuzhiyun #define GCC_UNIPHY2_BCR 66 304*4882a593Smuzhiyun #define GCC_CMN_12GPLL_BCR 67 305*4882a593Smuzhiyun #define GCC_QPIC_BCR 68 306*4882a593Smuzhiyun #define GCC_MDIO_BCR 69 307*4882a593Smuzhiyun #define GCC_PCIE1_TBU_BCR 70 308*4882a593Smuzhiyun #define GCC_WCSS_CORE_TBU_BCR 71 309*4882a593Smuzhiyun #define GCC_WCSS_Q6_TBU_BCR 72 310*4882a593Smuzhiyun #define GCC_USB0_TBU_BCR 73 311*4882a593Smuzhiyun #define GCC_USB1_TBU_BCR 74 312*4882a593Smuzhiyun #define GCC_PCIE0_TBU_BCR 75 313*4882a593Smuzhiyun #define GCC_NSS_NOC_TBU_BCR 76 314*4882a593Smuzhiyun #define GCC_PCIE0_BCR 77 315*4882a593Smuzhiyun #define GCC_PCIE0_PHY_BCR 78 316*4882a593Smuzhiyun #define GCC_PCIE0PHY_PHY_BCR 79 317*4882a593Smuzhiyun #define GCC_PCIE0_LINK_DOWN_BCR 80 318*4882a593Smuzhiyun #define GCC_PCIE1_BCR 81 319*4882a593Smuzhiyun #define GCC_PCIE1_PHY_BCR 82 320*4882a593Smuzhiyun #define GCC_PCIE1PHY_PHY_BCR 83 321*4882a593Smuzhiyun #define GCC_PCIE1_LINK_DOWN_BCR 84 322*4882a593Smuzhiyun #define GCC_DCC_BCR 85 323*4882a593Smuzhiyun #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 86 324*4882a593Smuzhiyun #define GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR 87 325*4882a593Smuzhiyun #define GCC_SMMU_CATS_BCR 88 326*4882a593Smuzhiyun #define GCC_UBI0_AXI_ARES 89 327*4882a593Smuzhiyun #define GCC_UBI0_AHB_ARES 90 328*4882a593Smuzhiyun #define GCC_UBI0_NC_AXI_ARES 91 329*4882a593Smuzhiyun #define GCC_UBI0_DBG_ARES 92 330*4882a593Smuzhiyun #define GCC_UBI0_CORE_CLAMP_ENABLE 93 331*4882a593Smuzhiyun #define GCC_UBI0_CLKRST_CLAMP_ENABLE 94 332*4882a593Smuzhiyun #define GCC_UBI1_AXI_ARES 95 333*4882a593Smuzhiyun #define GCC_UBI1_AHB_ARES 96 334*4882a593Smuzhiyun #define GCC_UBI1_NC_AXI_ARES 97 335*4882a593Smuzhiyun #define GCC_UBI1_DBG_ARES 98 336*4882a593Smuzhiyun #define GCC_UBI1_CORE_CLAMP_ENABLE 99 337*4882a593Smuzhiyun #define GCC_UBI1_CLKRST_CLAMP_ENABLE 100 338*4882a593Smuzhiyun #define GCC_NSS_CFG_ARES 101 339*4882a593Smuzhiyun #define GCC_NSS_IMEM_ARES 102 340*4882a593Smuzhiyun #define GCC_NSS_NOC_ARES 103 341*4882a593Smuzhiyun #define GCC_NSS_CRYPTO_ARES 104 342*4882a593Smuzhiyun #define GCC_NSS_CSR_ARES 105 343*4882a593Smuzhiyun #define GCC_NSS_CE_APB_ARES 106 344*4882a593Smuzhiyun #define GCC_NSS_CE_AXI_ARES 107 345*4882a593Smuzhiyun #define GCC_NSSNOC_CE_APB_ARES 108 346*4882a593Smuzhiyun #define GCC_NSSNOC_CE_AXI_ARES 109 347*4882a593Smuzhiyun #define GCC_NSSNOC_UBI0_AHB_ARES 110 348*4882a593Smuzhiyun #define GCC_NSSNOC_UBI1_AHB_ARES 111 349*4882a593Smuzhiyun #define GCC_NSSNOC_SNOC_ARES 112 350*4882a593Smuzhiyun #define GCC_NSSNOC_CRYPTO_ARES 113 351*4882a593Smuzhiyun #define GCC_NSSNOC_ATB_ARES 114 352*4882a593Smuzhiyun #define GCC_NSSNOC_QOSGEN_REF_ARES 115 353*4882a593Smuzhiyun #define GCC_NSSNOC_TIMEOUT_REF_ARES 116 354*4882a593Smuzhiyun #define GCC_PCIE0_PIPE_ARES 117 355*4882a593Smuzhiyun #define GCC_PCIE0_SLEEP_ARES 118 356*4882a593Smuzhiyun #define GCC_PCIE0_CORE_STICKY_ARES 119 357*4882a593Smuzhiyun #define GCC_PCIE0_AXI_MASTER_ARES 120 358*4882a593Smuzhiyun #define GCC_PCIE0_AXI_SLAVE_ARES 121 359*4882a593Smuzhiyun #define GCC_PCIE0_AHB_ARES 122 360*4882a593Smuzhiyun #define GCC_PCIE0_AXI_MASTER_STICKY_ARES 123 361*4882a593Smuzhiyun #define GCC_PCIE1_PIPE_ARES 124 362*4882a593Smuzhiyun #define GCC_PCIE1_SLEEP_ARES 125 363*4882a593Smuzhiyun #define GCC_PCIE1_CORE_STICKY_ARES 126 364*4882a593Smuzhiyun #define GCC_PCIE1_AXI_MASTER_ARES 127 365*4882a593Smuzhiyun #define GCC_PCIE1_AXI_SLAVE_ARES 128 366*4882a593Smuzhiyun #define GCC_PCIE1_AHB_ARES 129 367*4882a593Smuzhiyun #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 368*4882a593Smuzhiyun #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131 369*4882a593Smuzhiyun 370*4882a593Smuzhiyun #endif 371