1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_GCC_IPQ806X_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define AFAB_CLK_SRC 0 10*4882a593Smuzhiyun #define QDSS_STM_CLK 1 11*4882a593Smuzhiyun #define SCSS_A_CLK 2 12*4882a593Smuzhiyun #define SCSS_H_CLK 3 13*4882a593Smuzhiyun #define AFAB_CORE_CLK 4 14*4882a593Smuzhiyun #define SCSS_XO_SRC_CLK 5 15*4882a593Smuzhiyun #define AFAB_EBI1_CH0_A_CLK 6 16*4882a593Smuzhiyun #define AFAB_EBI1_CH1_A_CLK 7 17*4882a593Smuzhiyun #define AFAB_AXI_S0_FCLK 8 18*4882a593Smuzhiyun #define AFAB_AXI_S1_FCLK 9 19*4882a593Smuzhiyun #define AFAB_AXI_S2_FCLK 10 20*4882a593Smuzhiyun #define AFAB_AXI_S3_FCLK 11 21*4882a593Smuzhiyun #define AFAB_AXI_S4_FCLK 12 22*4882a593Smuzhiyun #define SFAB_CORE_CLK 13 23*4882a593Smuzhiyun #define SFAB_AXI_S0_FCLK 14 24*4882a593Smuzhiyun #define SFAB_AXI_S1_FCLK 15 25*4882a593Smuzhiyun #define SFAB_AXI_S2_FCLK 16 26*4882a593Smuzhiyun #define SFAB_AXI_S3_FCLK 17 27*4882a593Smuzhiyun #define SFAB_AXI_S4_FCLK 18 28*4882a593Smuzhiyun #define SFAB_AXI_S5_FCLK 19 29*4882a593Smuzhiyun #define SFAB_AHB_S0_FCLK 20 30*4882a593Smuzhiyun #define SFAB_AHB_S1_FCLK 21 31*4882a593Smuzhiyun #define SFAB_AHB_S2_FCLK 22 32*4882a593Smuzhiyun #define SFAB_AHB_S3_FCLK 23 33*4882a593Smuzhiyun #define SFAB_AHB_S4_FCLK 24 34*4882a593Smuzhiyun #define SFAB_AHB_S5_FCLK 25 35*4882a593Smuzhiyun #define SFAB_AHB_S6_FCLK 26 36*4882a593Smuzhiyun #define SFAB_AHB_S7_FCLK 27 37*4882a593Smuzhiyun #define QDSS_AT_CLK_SRC 28 38*4882a593Smuzhiyun #define QDSS_AT_CLK 29 39*4882a593Smuzhiyun #define QDSS_TRACECLKIN_CLK_SRC 30 40*4882a593Smuzhiyun #define QDSS_TRACECLKIN_CLK 31 41*4882a593Smuzhiyun #define QDSS_TSCTR_CLK_SRC 32 42*4882a593Smuzhiyun #define QDSS_TSCTR_CLK 33 43*4882a593Smuzhiyun #define SFAB_ADM0_M0_A_CLK 34 44*4882a593Smuzhiyun #define SFAB_ADM0_M1_A_CLK 35 45*4882a593Smuzhiyun #define SFAB_ADM0_M2_H_CLK 36 46*4882a593Smuzhiyun #define ADM0_CLK 37 47*4882a593Smuzhiyun #define ADM0_PBUS_CLK 38 48*4882a593Smuzhiyun #define IMEM0_A_CLK 39 49*4882a593Smuzhiyun #define QDSS_H_CLK 40 50*4882a593Smuzhiyun #define PCIE_A_CLK 41 51*4882a593Smuzhiyun #define PCIE_AUX_CLK 42 52*4882a593Smuzhiyun #define PCIE_H_CLK 43 53*4882a593Smuzhiyun #define PCIE_PHY_CLK 44 54*4882a593Smuzhiyun #define SFAB_CLK_SRC 45 55*4882a593Smuzhiyun #define SFAB_LPASS_Q6_A_CLK 46 56*4882a593Smuzhiyun #define SFAB_AFAB_M_A_CLK 47 57*4882a593Smuzhiyun #define AFAB_SFAB_M0_A_CLK 48 58*4882a593Smuzhiyun #define AFAB_SFAB_M1_A_CLK 49 59*4882a593Smuzhiyun #define SFAB_SATA_S_H_CLK 50 60*4882a593Smuzhiyun #define DFAB_CLK_SRC 51 61*4882a593Smuzhiyun #define DFAB_CLK 52 62*4882a593Smuzhiyun #define SFAB_DFAB_M_A_CLK 53 63*4882a593Smuzhiyun #define DFAB_SFAB_M_A_CLK 54 64*4882a593Smuzhiyun #define DFAB_SWAY0_H_CLK 55 65*4882a593Smuzhiyun #define DFAB_SWAY1_H_CLK 56 66*4882a593Smuzhiyun #define DFAB_ARB0_H_CLK 57 67*4882a593Smuzhiyun #define DFAB_ARB1_H_CLK 58 68*4882a593Smuzhiyun #define PPSS_H_CLK 59 69*4882a593Smuzhiyun #define PPSS_PROC_CLK 60 70*4882a593Smuzhiyun #define PPSS_TIMER0_CLK 61 71*4882a593Smuzhiyun #define PPSS_TIMER1_CLK 62 72*4882a593Smuzhiyun #define PMEM_A_CLK 63 73*4882a593Smuzhiyun #define DMA_BAM_H_CLK 64 74*4882a593Smuzhiyun #define SIC_H_CLK 65 75*4882a593Smuzhiyun #define SPS_TIC_H_CLK 66 76*4882a593Smuzhiyun #define CFPB_2X_CLK_SRC 67 77*4882a593Smuzhiyun #define CFPB_CLK 68 78*4882a593Smuzhiyun #define CFPB0_H_CLK 69 79*4882a593Smuzhiyun #define CFPB1_H_CLK 70 80*4882a593Smuzhiyun #define CFPB2_H_CLK 71 81*4882a593Smuzhiyun #define SFAB_CFPB_M_H_CLK 72 82*4882a593Smuzhiyun #define CFPB_MASTER_H_CLK 73 83*4882a593Smuzhiyun #define SFAB_CFPB_S_H_CLK 74 84*4882a593Smuzhiyun #define CFPB_SPLITTER_H_CLK 75 85*4882a593Smuzhiyun #define TSIF_H_CLK 76 86*4882a593Smuzhiyun #define TSIF_INACTIVITY_TIMERS_CLK 77 87*4882a593Smuzhiyun #define TSIF_REF_SRC 78 88*4882a593Smuzhiyun #define TSIF_REF_CLK 79 89*4882a593Smuzhiyun #define CE1_H_CLK 80 90*4882a593Smuzhiyun #define CE1_CORE_CLK 81 91*4882a593Smuzhiyun #define CE1_SLEEP_CLK 82 92*4882a593Smuzhiyun #define CE2_H_CLK 83 93*4882a593Smuzhiyun #define CE2_CORE_CLK 84 94*4882a593Smuzhiyun #define SFPB_H_CLK_SRC 85 95*4882a593Smuzhiyun #define SFPB_H_CLK 86 96*4882a593Smuzhiyun #define SFAB_SFPB_M_H_CLK 87 97*4882a593Smuzhiyun #define SFAB_SFPB_S_H_CLK 88 98*4882a593Smuzhiyun #define RPM_PROC_CLK 89 99*4882a593Smuzhiyun #define RPM_BUS_H_CLK 90 100*4882a593Smuzhiyun #define RPM_SLEEP_CLK 91 101*4882a593Smuzhiyun #define RPM_TIMER_CLK 92 102*4882a593Smuzhiyun #define RPM_MSG_RAM_H_CLK 93 103*4882a593Smuzhiyun #define PMIC_ARB0_H_CLK 94 104*4882a593Smuzhiyun #define PMIC_ARB1_H_CLK 95 105*4882a593Smuzhiyun #define PMIC_SSBI2_SRC 96 106*4882a593Smuzhiyun #define PMIC_SSBI2_CLK 97 107*4882a593Smuzhiyun #define SDC1_H_CLK 98 108*4882a593Smuzhiyun #define SDC2_H_CLK 99 109*4882a593Smuzhiyun #define SDC3_H_CLK 100 110*4882a593Smuzhiyun #define SDC4_H_CLK 101 111*4882a593Smuzhiyun #define SDC1_SRC 102 112*4882a593Smuzhiyun #define SDC1_CLK 103 113*4882a593Smuzhiyun #define SDC2_SRC 104 114*4882a593Smuzhiyun #define SDC2_CLK 105 115*4882a593Smuzhiyun #define SDC3_SRC 106 116*4882a593Smuzhiyun #define SDC3_CLK 107 117*4882a593Smuzhiyun #define SDC4_SRC 108 118*4882a593Smuzhiyun #define SDC4_CLK 109 119*4882a593Smuzhiyun #define USB_HS1_H_CLK 110 120*4882a593Smuzhiyun #define USB_HS1_XCVR_SRC 111 121*4882a593Smuzhiyun #define USB_HS1_XCVR_CLK 112 122*4882a593Smuzhiyun #define USB_HSIC_H_CLK 113 123*4882a593Smuzhiyun #define USB_HSIC_XCVR_SRC 114 124*4882a593Smuzhiyun #define USB_HSIC_XCVR_CLK 115 125*4882a593Smuzhiyun #define USB_HSIC_SYSTEM_CLK_SRC 116 126*4882a593Smuzhiyun #define USB_HSIC_SYSTEM_CLK 117 127*4882a593Smuzhiyun #define CFPB0_C0_H_CLK 118 128*4882a593Smuzhiyun #define CFPB0_D0_H_CLK 119 129*4882a593Smuzhiyun #define CFPB0_C1_H_CLK 120 130*4882a593Smuzhiyun #define CFPB0_D1_H_CLK 121 131*4882a593Smuzhiyun #define USB_FS1_H_CLK 122 132*4882a593Smuzhiyun #define USB_FS1_XCVR_SRC 123 133*4882a593Smuzhiyun #define USB_FS1_XCVR_CLK 124 134*4882a593Smuzhiyun #define USB_FS1_SYSTEM_CLK 125 135*4882a593Smuzhiyun #define GSBI_COMMON_SIM_SRC 126 136*4882a593Smuzhiyun #define GSBI1_H_CLK 127 137*4882a593Smuzhiyun #define GSBI2_H_CLK 128 138*4882a593Smuzhiyun #define GSBI3_H_CLK 129 139*4882a593Smuzhiyun #define GSBI4_H_CLK 130 140*4882a593Smuzhiyun #define GSBI5_H_CLK 131 141*4882a593Smuzhiyun #define GSBI6_H_CLK 132 142*4882a593Smuzhiyun #define GSBI7_H_CLK 133 143*4882a593Smuzhiyun #define GSBI1_QUP_SRC 134 144*4882a593Smuzhiyun #define GSBI1_QUP_CLK 135 145*4882a593Smuzhiyun #define GSBI2_QUP_SRC 136 146*4882a593Smuzhiyun #define GSBI2_QUP_CLK 137 147*4882a593Smuzhiyun #define GSBI3_QUP_SRC 138 148*4882a593Smuzhiyun #define GSBI3_QUP_CLK 139 149*4882a593Smuzhiyun #define GSBI4_QUP_SRC 140 150*4882a593Smuzhiyun #define GSBI4_QUP_CLK 141 151*4882a593Smuzhiyun #define GSBI5_QUP_SRC 142 152*4882a593Smuzhiyun #define GSBI5_QUP_CLK 143 153*4882a593Smuzhiyun #define GSBI6_QUP_SRC 144 154*4882a593Smuzhiyun #define GSBI6_QUP_CLK 145 155*4882a593Smuzhiyun #define GSBI7_QUP_SRC 146 156*4882a593Smuzhiyun #define GSBI7_QUP_CLK 147 157*4882a593Smuzhiyun #define GSBI1_UART_SRC 148 158*4882a593Smuzhiyun #define GSBI1_UART_CLK 149 159*4882a593Smuzhiyun #define GSBI2_UART_SRC 150 160*4882a593Smuzhiyun #define GSBI2_UART_CLK 151 161*4882a593Smuzhiyun #define GSBI3_UART_SRC 152 162*4882a593Smuzhiyun #define GSBI3_UART_CLK 153 163*4882a593Smuzhiyun #define GSBI4_UART_SRC 154 164*4882a593Smuzhiyun #define GSBI4_UART_CLK 155 165*4882a593Smuzhiyun #define GSBI5_UART_SRC 156 166*4882a593Smuzhiyun #define GSBI5_UART_CLK 157 167*4882a593Smuzhiyun #define GSBI6_UART_SRC 158 168*4882a593Smuzhiyun #define GSBI6_UART_CLK 159 169*4882a593Smuzhiyun #define GSBI7_UART_SRC 160 170*4882a593Smuzhiyun #define GSBI7_UART_CLK 161 171*4882a593Smuzhiyun #define GSBI1_SIM_CLK 162 172*4882a593Smuzhiyun #define GSBI2_SIM_CLK 163 173*4882a593Smuzhiyun #define GSBI3_SIM_CLK 164 174*4882a593Smuzhiyun #define GSBI4_SIM_CLK 165 175*4882a593Smuzhiyun #define GSBI5_SIM_CLK 166 176*4882a593Smuzhiyun #define GSBI6_SIM_CLK 167 177*4882a593Smuzhiyun #define GSBI7_SIM_CLK 168 178*4882a593Smuzhiyun #define USB_HSIC_HSIC_CLK_SRC 169 179*4882a593Smuzhiyun #define USB_HSIC_HSIC_CLK 170 180*4882a593Smuzhiyun #define USB_HSIC_HSIO_CAL_CLK 171 181*4882a593Smuzhiyun #define SPDM_CFG_H_CLK 172 182*4882a593Smuzhiyun #define SPDM_MSTR_H_CLK 173 183*4882a593Smuzhiyun #define SPDM_FF_CLK_SRC 174 184*4882a593Smuzhiyun #define SPDM_FF_CLK 175 185*4882a593Smuzhiyun #define SEC_CTRL_CLK 176 186*4882a593Smuzhiyun #define SEC_CTRL_ACC_CLK_SRC 177 187*4882a593Smuzhiyun #define SEC_CTRL_ACC_CLK 178 188*4882a593Smuzhiyun #define TLMM_H_CLK 179 189*4882a593Smuzhiyun #define TLMM_CLK 180 190*4882a593Smuzhiyun #define SATA_H_CLK 181 191*4882a593Smuzhiyun #define SATA_CLK_SRC 182 192*4882a593Smuzhiyun #define SATA_RXOOB_CLK 183 193*4882a593Smuzhiyun #define SATA_PMALIVE_CLK 184 194*4882a593Smuzhiyun #define SATA_PHY_REF_CLK 185 195*4882a593Smuzhiyun #define SATA_A_CLK 186 196*4882a593Smuzhiyun #define SATA_PHY_CFG_CLK 187 197*4882a593Smuzhiyun #define TSSC_CLK_SRC 188 198*4882a593Smuzhiyun #define TSSC_CLK 189 199*4882a593Smuzhiyun #define PDM_SRC 190 200*4882a593Smuzhiyun #define PDM_CLK 191 201*4882a593Smuzhiyun #define GP0_SRC 192 202*4882a593Smuzhiyun #define GP0_CLK 193 203*4882a593Smuzhiyun #define GP1_SRC 194 204*4882a593Smuzhiyun #define GP1_CLK 195 205*4882a593Smuzhiyun #define GP2_SRC 196 206*4882a593Smuzhiyun #define GP2_CLK 197 207*4882a593Smuzhiyun #define MPM_CLK 198 208*4882a593Smuzhiyun #define EBI1_CLK_SRC 199 209*4882a593Smuzhiyun #define EBI1_CH0_CLK 200 210*4882a593Smuzhiyun #define EBI1_CH1_CLK 201 211*4882a593Smuzhiyun #define EBI1_2X_CLK 202 212*4882a593Smuzhiyun #define EBI1_CH0_DQ_CLK 203 213*4882a593Smuzhiyun #define EBI1_CH1_DQ_CLK 204 214*4882a593Smuzhiyun #define EBI1_CH0_CA_CLK 205 215*4882a593Smuzhiyun #define EBI1_CH1_CA_CLK 206 216*4882a593Smuzhiyun #define EBI1_XO_CLK 207 217*4882a593Smuzhiyun #define SFAB_SMPSS_S_H_CLK 208 218*4882a593Smuzhiyun #define PRNG_SRC 209 219*4882a593Smuzhiyun #define PRNG_CLK 210 220*4882a593Smuzhiyun #define PXO_SRC 211 221*4882a593Smuzhiyun #define SPDM_CY_PORT0_CLK 212 222*4882a593Smuzhiyun #define SPDM_CY_PORT1_CLK 213 223*4882a593Smuzhiyun #define SPDM_CY_PORT2_CLK 214 224*4882a593Smuzhiyun #define SPDM_CY_PORT3_CLK 215 225*4882a593Smuzhiyun #define SPDM_CY_PORT4_CLK 216 226*4882a593Smuzhiyun #define SPDM_CY_PORT5_CLK 217 227*4882a593Smuzhiyun #define SPDM_CY_PORT6_CLK 218 228*4882a593Smuzhiyun #define SPDM_CY_PORT7_CLK 219 229*4882a593Smuzhiyun #define PLL0 220 230*4882a593Smuzhiyun #define PLL0_VOTE 221 231*4882a593Smuzhiyun #define PLL3 222 232*4882a593Smuzhiyun #define PLL3_VOTE 223 233*4882a593Smuzhiyun #define PLL4_VOTE 225 234*4882a593Smuzhiyun #define PLL8 226 235*4882a593Smuzhiyun #define PLL8_VOTE 227 236*4882a593Smuzhiyun #define PLL9 228 237*4882a593Smuzhiyun #define PLL10 229 238*4882a593Smuzhiyun #define PLL11 230 239*4882a593Smuzhiyun #define PLL12 231 240*4882a593Smuzhiyun #define PLL14 232 241*4882a593Smuzhiyun #define PLL14_VOTE 233 242*4882a593Smuzhiyun #define PLL18 234 243*4882a593Smuzhiyun #define CE5_SRC 235 244*4882a593Smuzhiyun #define CE5_H_CLK 236 245*4882a593Smuzhiyun #define CE5_CORE_CLK 237 246*4882a593Smuzhiyun #define CE3_SLEEP_CLK 238 247*4882a593Smuzhiyun #define SFAB_AHB_S8_FCLK 239 248*4882a593Smuzhiyun #define SPDM_CY_PORT8_CLK 246 249*4882a593Smuzhiyun #define PCIE_ALT_REF_SRC 247 250*4882a593Smuzhiyun #define PCIE_ALT_REF_CLK 248 251*4882a593Smuzhiyun #define PCIE_1_A_CLK 249 252*4882a593Smuzhiyun #define PCIE_1_AUX_CLK 250 253*4882a593Smuzhiyun #define PCIE_1_H_CLK 251 254*4882a593Smuzhiyun #define PCIE_1_PHY_CLK 252 255*4882a593Smuzhiyun #define PCIE_1_ALT_REF_SRC 253 256*4882a593Smuzhiyun #define PCIE_1_ALT_REF_CLK 254 257*4882a593Smuzhiyun #define PCIE_2_A_CLK 255 258*4882a593Smuzhiyun #define PCIE_2_AUX_CLK 256 259*4882a593Smuzhiyun #define PCIE_2_H_CLK 257 260*4882a593Smuzhiyun #define PCIE_2_PHY_CLK 258 261*4882a593Smuzhiyun #define PCIE_2_ALT_REF_SRC 259 262*4882a593Smuzhiyun #define PCIE_2_ALT_REF_CLK 260 263*4882a593Smuzhiyun #define EBI2_CLK 261 264*4882a593Smuzhiyun #define USB30_SLEEP_CLK 262 265*4882a593Smuzhiyun #define USB30_UTMI_SRC 263 266*4882a593Smuzhiyun #define USB30_0_UTMI_CLK 264 267*4882a593Smuzhiyun #define USB30_1_UTMI_CLK 265 268*4882a593Smuzhiyun #define USB30_MASTER_SRC 266 269*4882a593Smuzhiyun #define USB30_0_MASTER_CLK 267 270*4882a593Smuzhiyun #define USB30_1_MASTER_CLK 268 271*4882a593Smuzhiyun #define GMAC_CORE1_CLK_SRC 269 272*4882a593Smuzhiyun #define GMAC_CORE2_CLK_SRC 270 273*4882a593Smuzhiyun #define GMAC_CORE3_CLK_SRC 271 274*4882a593Smuzhiyun #define GMAC_CORE4_CLK_SRC 272 275*4882a593Smuzhiyun #define GMAC_CORE1_CLK 273 276*4882a593Smuzhiyun #define GMAC_CORE2_CLK 274 277*4882a593Smuzhiyun #define GMAC_CORE3_CLK 275 278*4882a593Smuzhiyun #define GMAC_CORE4_CLK 276 279*4882a593Smuzhiyun #define UBI32_CORE1_CLK_SRC 277 280*4882a593Smuzhiyun #define UBI32_CORE2_CLK_SRC 278 281*4882a593Smuzhiyun #define UBI32_CORE1_CLK 279 282*4882a593Smuzhiyun #define UBI32_CORE2_CLK 280 283*4882a593Smuzhiyun #define EBI2_AON_CLK 281 284*4882a593Smuzhiyun #define NSSTCM_CLK_SRC 282 285*4882a593Smuzhiyun #define NSSTCM_CLK 283 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun #endif 288