1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define GPLL0 0 10*4882a593Smuzhiyun #define UBI32_PLL 1 11*4882a593Smuzhiyun #define GPLL6 2 12*4882a593Smuzhiyun #define GPLL4 3 13*4882a593Smuzhiyun #define PCNOC_BFDCD_CLK_SRC 4 14*4882a593Smuzhiyun #define GPLL2 5 15*4882a593Smuzhiyun #define NSS_CRYPTO_PLL 6 16*4882a593Smuzhiyun #define NSS_PPE_CLK_SRC 7 17*4882a593Smuzhiyun #define GCC_XO_CLK_SRC 8 18*4882a593Smuzhiyun #define NSS_CE_CLK_SRC 9 19*4882a593Smuzhiyun #define GCC_SLEEP_CLK_SRC 10 20*4882a593Smuzhiyun #define APSS_AHB_CLK_SRC 11 21*4882a593Smuzhiyun #define NSS_PORT5_RX_CLK_SRC 12 22*4882a593Smuzhiyun #define NSS_PORT5_TX_CLK_SRC 13 23*4882a593Smuzhiyun #define PCIE0_AXI_CLK_SRC 14 24*4882a593Smuzhiyun #define USB0_MASTER_CLK_SRC 15 25*4882a593Smuzhiyun #define APSS_AHB_POSTDIV_CLK_SRC 16 26*4882a593Smuzhiyun #define NSS_PORT1_RX_CLK_SRC 17 27*4882a593Smuzhiyun #define NSS_PORT1_TX_CLK_SRC 18 28*4882a593Smuzhiyun #define NSS_PORT2_RX_CLK_SRC 19 29*4882a593Smuzhiyun #define NSS_PORT2_TX_CLK_SRC 20 30*4882a593Smuzhiyun #define NSS_PORT3_RX_CLK_SRC 21 31*4882a593Smuzhiyun #define NSS_PORT3_TX_CLK_SRC 22 32*4882a593Smuzhiyun #define NSS_PORT4_RX_CLK_SRC 23 33*4882a593Smuzhiyun #define NSS_PORT4_TX_CLK_SRC 24 34*4882a593Smuzhiyun #define NSS_PORT5_RX_DIV_CLK_SRC 25 35*4882a593Smuzhiyun #define NSS_PORT5_TX_DIV_CLK_SRC 26 36*4882a593Smuzhiyun #define APSS_AXI_CLK_SRC 27 37*4882a593Smuzhiyun #define NSS_CRYPTO_CLK_SRC 28 38*4882a593Smuzhiyun #define NSS_PORT1_RX_DIV_CLK_SRC 29 39*4882a593Smuzhiyun #define NSS_PORT1_TX_DIV_CLK_SRC 30 40*4882a593Smuzhiyun #define NSS_PORT2_RX_DIV_CLK_SRC 31 41*4882a593Smuzhiyun #define NSS_PORT2_TX_DIV_CLK_SRC 32 42*4882a593Smuzhiyun #define NSS_PORT3_RX_DIV_CLK_SRC 33 43*4882a593Smuzhiyun #define NSS_PORT3_TX_DIV_CLK_SRC 34 44*4882a593Smuzhiyun #define NSS_PORT4_RX_DIV_CLK_SRC 35 45*4882a593Smuzhiyun #define NSS_PORT4_TX_DIV_CLK_SRC 36 46*4882a593Smuzhiyun #define NSS_UBI0_CLK_SRC 37 47*4882a593Smuzhiyun #define BLSP1_QUP1_I2C_APPS_CLK_SRC 38 48*4882a593Smuzhiyun #define BLSP1_QUP1_SPI_APPS_CLK_SRC 39 49*4882a593Smuzhiyun #define BLSP1_QUP2_I2C_APPS_CLK_SRC 40 50*4882a593Smuzhiyun #define BLSP1_QUP2_SPI_APPS_CLK_SRC 41 51*4882a593Smuzhiyun #define BLSP1_QUP3_I2C_APPS_CLK_SRC 42 52*4882a593Smuzhiyun #define BLSP1_QUP3_SPI_APPS_CLK_SRC 43 53*4882a593Smuzhiyun #define BLSP1_QUP4_I2C_APPS_CLK_SRC 44 54*4882a593Smuzhiyun #define BLSP1_QUP4_SPI_APPS_CLK_SRC 45 55*4882a593Smuzhiyun #define BLSP1_QUP5_I2C_APPS_CLK_SRC 46 56*4882a593Smuzhiyun #define BLSP1_QUP5_SPI_APPS_CLK_SRC 47 57*4882a593Smuzhiyun #define BLSP1_QUP6_I2C_APPS_CLK_SRC 48 58*4882a593Smuzhiyun #define BLSP1_QUP6_SPI_APPS_CLK_SRC 49 59*4882a593Smuzhiyun #define BLSP1_UART1_APPS_CLK_SRC 50 60*4882a593Smuzhiyun #define BLSP1_UART2_APPS_CLK_SRC 51 61*4882a593Smuzhiyun #define BLSP1_UART3_APPS_CLK_SRC 52 62*4882a593Smuzhiyun #define BLSP1_UART4_APPS_CLK_SRC 53 63*4882a593Smuzhiyun #define BLSP1_UART5_APPS_CLK_SRC 54 64*4882a593Smuzhiyun #define BLSP1_UART6_APPS_CLK_SRC 55 65*4882a593Smuzhiyun #define CRYPTO_CLK_SRC 56 66*4882a593Smuzhiyun #define NSS_UBI0_DIV_CLK_SRC 57 67*4882a593Smuzhiyun #define PCIE0_AUX_CLK_SRC 58 68*4882a593Smuzhiyun #define PCIE0_PIPE_CLK_SRC 59 69*4882a593Smuzhiyun #define SDCC1_APPS_CLK_SRC 60 70*4882a593Smuzhiyun #define USB0_AUX_CLK_SRC 61 71*4882a593Smuzhiyun #define USB0_MOCK_UTMI_CLK_SRC 62 72*4882a593Smuzhiyun #define USB0_PIPE_CLK_SRC 63 73*4882a593Smuzhiyun #define USB1_MOCK_UTMI_CLK_SRC 64 74*4882a593Smuzhiyun #define GCC_APSS_AHB_CLK 65 75*4882a593Smuzhiyun #define GCC_APSS_AXI_CLK 66 76*4882a593Smuzhiyun #define GCC_BLSP1_AHB_CLK 67 77*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_I2C_APPS_CLK 68 78*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_SPI_APPS_CLK 69 79*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_I2C_APPS_CLK 70 80*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_SPI_APPS_CLK 71 81*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_I2C_APPS_CLK 72 82*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_SPI_APPS_CLK 73 83*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_I2C_APPS_CLK 74 84*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_SPI_APPS_CLK 75 85*4882a593Smuzhiyun #define GCC_BLSP1_QUP5_I2C_APPS_CLK 76 86*4882a593Smuzhiyun #define GCC_BLSP1_QUP5_SPI_APPS_CLK 77 87*4882a593Smuzhiyun #define GCC_BLSP1_QUP6_I2C_APPS_CLK 78 88*4882a593Smuzhiyun #define GCC_BLSP1_QUP6_SPI_APPS_CLK 79 89*4882a593Smuzhiyun #define GCC_BLSP1_UART1_APPS_CLK 80 90*4882a593Smuzhiyun #define GCC_BLSP1_UART2_APPS_CLK 81 91*4882a593Smuzhiyun #define GCC_BLSP1_UART3_APPS_CLK 82 92*4882a593Smuzhiyun #define GCC_BLSP1_UART4_APPS_CLK 83 93*4882a593Smuzhiyun #define GCC_BLSP1_UART5_APPS_CLK 84 94*4882a593Smuzhiyun #define GCC_BLSP1_UART6_APPS_CLK 85 95*4882a593Smuzhiyun #define GCC_CRYPTO_AHB_CLK 86 96*4882a593Smuzhiyun #define GCC_CRYPTO_AXI_CLK 87 97*4882a593Smuzhiyun #define GCC_CRYPTO_CLK 88 98*4882a593Smuzhiyun #define GCC_XO_CLK 89 99*4882a593Smuzhiyun #define GCC_XO_DIV4_CLK 90 100*4882a593Smuzhiyun #define GCC_MDIO_AHB_CLK 91 101*4882a593Smuzhiyun #define GCC_CRYPTO_PPE_CLK 92 102*4882a593Smuzhiyun #define GCC_NSS_CE_APB_CLK 93 103*4882a593Smuzhiyun #define GCC_NSS_CE_AXI_CLK 94 104*4882a593Smuzhiyun #define GCC_NSS_CFG_CLK 95 105*4882a593Smuzhiyun #define GCC_NSS_CRYPTO_CLK 96 106*4882a593Smuzhiyun #define GCC_NSS_CSR_CLK 97 107*4882a593Smuzhiyun #define GCC_NSS_EDMA_CFG_CLK 98 108*4882a593Smuzhiyun #define GCC_NSS_EDMA_CLK 99 109*4882a593Smuzhiyun #define GCC_NSS_NOC_CLK 100 110*4882a593Smuzhiyun #define GCC_NSS_PORT1_RX_CLK 101 111*4882a593Smuzhiyun #define GCC_NSS_PORT1_TX_CLK 102 112*4882a593Smuzhiyun #define GCC_NSS_PORT2_RX_CLK 103 113*4882a593Smuzhiyun #define GCC_NSS_PORT2_TX_CLK 104 114*4882a593Smuzhiyun #define GCC_NSS_PORT3_RX_CLK 105 115*4882a593Smuzhiyun #define GCC_NSS_PORT3_TX_CLK 106 116*4882a593Smuzhiyun #define GCC_NSS_PORT4_RX_CLK 107 117*4882a593Smuzhiyun #define GCC_NSS_PORT4_TX_CLK 108 118*4882a593Smuzhiyun #define GCC_NSS_PORT5_RX_CLK 109 119*4882a593Smuzhiyun #define GCC_NSS_PORT5_TX_CLK 110 120*4882a593Smuzhiyun #define GCC_NSS_PPE_CFG_CLK 111 121*4882a593Smuzhiyun #define GCC_NSS_PPE_CLK 112 122*4882a593Smuzhiyun #define GCC_NSS_PPE_IPE_CLK 113 123*4882a593Smuzhiyun #define GCC_NSS_PTP_REF_CLK 114 124*4882a593Smuzhiyun #define GCC_NSSNOC_CE_APB_CLK 115 125*4882a593Smuzhiyun #define GCC_NSSNOC_CE_AXI_CLK 116 126*4882a593Smuzhiyun #define GCC_NSSNOC_CRYPTO_CLK 117 127*4882a593Smuzhiyun #define GCC_NSSNOC_PPE_CFG_CLK 118 128*4882a593Smuzhiyun #define GCC_NSSNOC_PPE_CLK 119 129*4882a593Smuzhiyun #define GCC_NSSNOC_QOSGEN_REF_CLK 120 130*4882a593Smuzhiyun #define GCC_NSSNOC_TIMEOUT_REF_CLK 121 131*4882a593Smuzhiyun #define GCC_NSSNOC_UBI0_AHB_CLK 122 132*4882a593Smuzhiyun #define GCC_PORT1_MAC_CLK 123 133*4882a593Smuzhiyun #define GCC_PORT2_MAC_CLK 124 134*4882a593Smuzhiyun #define GCC_PORT3_MAC_CLK 125 135*4882a593Smuzhiyun #define GCC_PORT4_MAC_CLK 126 136*4882a593Smuzhiyun #define GCC_PORT5_MAC_CLK 127 137*4882a593Smuzhiyun #define GCC_UBI0_AHB_CLK 128 138*4882a593Smuzhiyun #define GCC_UBI0_AXI_CLK 129 139*4882a593Smuzhiyun #define GCC_UBI0_CORE_CLK 130 140*4882a593Smuzhiyun #define GCC_PCIE0_AHB_CLK 131 141*4882a593Smuzhiyun #define GCC_PCIE0_AUX_CLK 132 142*4882a593Smuzhiyun #define GCC_PCIE0_AXI_M_CLK 133 143*4882a593Smuzhiyun #define GCC_PCIE0_AXI_S_CLK 134 144*4882a593Smuzhiyun #define GCC_PCIE0_PIPE_CLK 135 145*4882a593Smuzhiyun #define GCC_PRNG_AHB_CLK 136 146*4882a593Smuzhiyun #define GCC_QPIC_AHB_CLK 137 147*4882a593Smuzhiyun #define GCC_QPIC_CLK 138 148*4882a593Smuzhiyun #define GCC_SDCC1_AHB_CLK 139 149*4882a593Smuzhiyun #define GCC_SDCC1_APPS_CLK 140 150*4882a593Smuzhiyun #define GCC_UNIPHY0_AHB_CLK 141 151*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT1_RX_CLK 142 152*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT1_TX_CLK 143 153*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT2_RX_CLK 144 154*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT2_TX_CLK 145 155*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT3_RX_CLK 146 156*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT3_TX_CLK 147 157*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT4_RX_CLK 148 158*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT4_TX_CLK 149 159*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT5_RX_CLK 150 160*4882a593Smuzhiyun #define GCC_UNIPHY0_PORT5_TX_CLK 151 161*4882a593Smuzhiyun #define GCC_UNIPHY0_SYS_CLK 152 162*4882a593Smuzhiyun #define GCC_UNIPHY1_AHB_CLK 153 163*4882a593Smuzhiyun #define GCC_UNIPHY1_PORT5_RX_CLK 154 164*4882a593Smuzhiyun #define GCC_UNIPHY1_PORT5_TX_CLK 155 165*4882a593Smuzhiyun #define GCC_UNIPHY1_SYS_CLK 156 166*4882a593Smuzhiyun #define GCC_USB0_AUX_CLK 157 167*4882a593Smuzhiyun #define GCC_USB0_MASTER_CLK 158 168*4882a593Smuzhiyun #define GCC_USB0_MOCK_UTMI_CLK 159 169*4882a593Smuzhiyun #define GCC_USB0_PHY_CFG_AHB_CLK 160 170*4882a593Smuzhiyun #define GCC_USB0_PIPE_CLK 161 171*4882a593Smuzhiyun #define GCC_USB0_SLEEP_CLK 162 172*4882a593Smuzhiyun #define GCC_USB1_MASTER_CLK 163 173*4882a593Smuzhiyun #define GCC_USB1_MOCK_UTMI_CLK 164 174*4882a593Smuzhiyun #define GCC_USB1_PHY_CFG_AHB_CLK 165 175*4882a593Smuzhiyun #define GCC_USB1_SLEEP_CLK 166 176*4882a593Smuzhiyun #define GP1_CLK_SRC 167 177*4882a593Smuzhiyun #define GP2_CLK_SRC 168 178*4882a593Smuzhiyun #define GP3_CLK_SRC 169 179*4882a593Smuzhiyun #define GCC_GP1_CLK 170 180*4882a593Smuzhiyun #define GCC_GP2_CLK 171 181*4882a593Smuzhiyun #define GCC_GP3_CLK 172 182*4882a593Smuzhiyun #define SYSTEM_NOC_BFDCD_CLK_SRC 173 183*4882a593Smuzhiyun #define GCC_NSSNOC_SNOC_CLK 174 184*4882a593Smuzhiyun #define GCC_UBI0_NC_AXI_CLK 175 185*4882a593Smuzhiyun #define GCC_UBI1_NC_AXI_CLK 176 186*4882a593Smuzhiyun #define GPLL0_MAIN 177 187*4882a593Smuzhiyun #define UBI32_PLL_MAIN 178 188*4882a593Smuzhiyun #define GPLL6_MAIN 179 189*4882a593Smuzhiyun #define GPLL4_MAIN 180 190*4882a593Smuzhiyun #define GPLL2_MAIN 181 191*4882a593Smuzhiyun #define NSS_CRYPTO_PLL_MAIN 182 192*4882a593Smuzhiyun #define GCC_CMN_12GPLL_AHB_CLK 183 193*4882a593Smuzhiyun #define GCC_CMN_12GPLL_SYS_CLK 184 194*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 185 195*4882a593Smuzhiyun #define GCC_SYS_NOC_USB0_AXI_CLK 186 196*4882a593Smuzhiyun #define GCC_SYS_NOC_PCIE0_AXI_CLK 187 197*4882a593Smuzhiyun #define QDSS_TSCTR_CLK_SRC 188 198*4882a593Smuzhiyun #define QDSS_AT_CLK_SRC 189 199*4882a593Smuzhiyun #define GCC_QDSS_AT_CLK 190 200*4882a593Smuzhiyun #define GCC_QDSS_DAP_CLK 191 201*4882a593Smuzhiyun #define ADSS_PWM_CLK_SRC 192 202*4882a593Smuzhiyun #define GCC_ADSS_PWM_CLK 193 203*4882a593Smuzhiyun #define SDCC1_ICE_CORE_CLK_SRC 194 204*4882a593Smuzhiyun #define GCC_SDCC1_ICE_CORE_CLK 195 205*4882a593Smuzhiyun #define GCC_DCC_CLK 196 206*4882a593Smuzhiyun #define PCIE0_RCHNG_CLK_SRC 197 207*4882a593Smuzhiyun #define GCC_PCIE0_AXI_S_BRIDGE_CLK 198 208*4882a593Smuzhiyun #define PCIE0_RCHNG_CLK 199 209*4882a593Smuzhiyun #define UBI32_MEM_NOC_BFDCD_CLK_SRC 200 210*4882a593Smuzhiyun #define WCSS_AHB_CLK_SRC 201 211*4882a593Smuzhiyun #define Q6_AXI_CLK_SRC 202 212*4882a593Smuzhiyun #define GCC_Q6SS_PCLKDBG_CLK 203 213*4882a593Smuzhiyun #define GCC_Q6_TSCTR_1TO2_CLK 204 214*4882a593Smuzhiyun #define GCC_WCSS_CORE_TBU_CLK 205 215*4882a593Smuzhiyun #define GCC_WCSS_AXI_M_CLK 206 216*4882a593Smuzhiyun #define GCC_SYS_NOC_WCSS_AHB_CLK 207 217*4882a593Smuzhiyun #define GCC_Q6_AXIM_CLK 208 218*4882a593Smuzhiyun #define GCC_Q6SS_ATBM_CLK 209 219*4882a593Smuzhiyun #define GCC_WCSS_Q6_TBU_CLK 210 220*4882a593Smuzhiyun #define GCC_Q6_AXIM2_CLK 211 221*4882a593Smuzhiyun #define GCC_Q6_AHB_CLK 212 222*4882a593Smuzhiyun #define GCC_Q6_AHB_S_CLK 213 223*4882a593Smuzhiyun #define GCC_WCSS_DBG_IFC_APB_CLK 214 224*4882a593Smuzhiyun #define GCC_WCSS_DBG_IFC_ATB_CLK 215 225*4882a593Smuzhiyun #define GCC_WCSS_DBG_IFC_NTS_CLK 216 226*4882a593Smuzhiyun #define GCC_WCSS_DBG_IFC_DAPBUS_CLK 217 227*4882a593Smuzhiyun #define GCC_WCSS_DBG_IFC_APB_BDG_CLK 218 228*4882a593Smuzhiyun #define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 219 229*4882a593Smuzhiyun #define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 220 230*4882a593Smuzhiyun #define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 221 231*4882a593Smuzhiyun #define GCC_WCSS_ECAHB_CLK 222 232*4882a593Smuzhiyun #define GCC_WCSS_ACMT_CLK 223 233*4882a593Smuzhiyun #define GCC_WCSS_AHB_S_CLK 224 234*4882a593Smuzhiyun #define GCC_RBCPR_WCSS_CLK 225 235*4882a593Smuzhiyun #define RBCPR_WCSS_CLK_SRC 226 236*4882a593Smuzhiyun #define GCC_RBCPR_WCSS_AHB_CLK 227 237*4882a593Smuzhiyun #define GCC_LPASS_CORE_AXIM_CLK 228 238*4882a593Smuzhiyun #define GCC_LPASS_SNOC_CFG_CLK 229 239*4882a593Smuzhiyun #define GCC_LPASS_Q6_AXIM_CLK 230 240*4882a593Smuzhiyun #define GCC_LPASS_Q6_ATBM_AT_CLK 231 241*4882a593Smuzhiyun #define GCC_LPASS_Q6_PCLKDBG_CLK 232 242*4882a593Smuzhiyun #define GCC_LPASS_Q6SS_TSCTR_1TO2_CLK 233 243*4882a593Smuzhiyun #define GCC_LPASS_Q6SS_TRIG_CLK 234 244*4882a593Smuzhiyun #define GCC_LPASS_TBU_CLK 235 245*4882a593Smuzhiyun #define LPASS_CORE_AXIM_CLK_SRC 236 246*4882a593Smuzhiyun #define LPASS_SNOC_CFG_CLK_SRC 237 247*4882a593Smuzhiyun #define LPASS_Q6_AXIM_CLK_SRC 238 248*4882a593Smuzhiyun #define GCC_PCNOC_LPASS_CLK 239 249*4882a593Smuzhiyun #define GCC_UBI0_UTCM_CLK 240 250*4882a593Smuzhiyun #define SNOC_NSSNOC_BFDCD_CLK_SRC 241 251*4882a593Smuzhiyun #define GCC_SNOC_NSSNOC_CLK 242 252*4882a593Smuzhiyun #define GCC_MEM_NOC_Q6_AXI_CLK 243 253*4882a593Smuzhiyun #define GCC_MEM_NOC_UBI32_CLK 244 254*4882a593Smuzhiyun #define GCC_MEM_NOC_LPASS_CLK 245 255*4882a593Smuzhiyun #define GCC_SNOC_LPASS_CFG_CLK 246 256*4882a593Smuzhiyun #define GCC_SYS_NOC_QDSS_STM_AXI_CLK 247 257*4882a593Smuzhiyun #define GCC_QDSS_STM_CLK 248 258*4882a593Smuzhiyun #define GCC_QDSS_TRACECLKIN_CLK 249 259*4882a593Smuzhiyun #define QDSS_STM_CLK_SRC 250 260*4882a593Smuzhiyun #define QDSS_TRACECLKIN_CLK_SRC 251 261*4882a593Smuzhiyun #define GCC_NSSNOC_ATB_CLK 252 262*4882a593Smuzhiyun #endif 263