1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* DISP_CC clock registers */ 10*4882a593Smuzhiyun #define DISP_CC_MDSS_AHB_CLK 0 11*4882a593Smuzhiyun #define DISP_CC_MDSS_AHB_CLK_SRC 1 12*4882a593Smuzhiyun #define DISP_CC_MDSS_BYTE0_CLK 2 13*4882a593Smuzhiyun #define DISP_CC_MDSS_BYTE0_CLK_SRC 3 14*4882a593Smuzhiyun #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4 15*4882a593Smuzhiyun #define DISP_CC_MDSS_BYTE0_INTF_CLK 5 16*4882a593Smuzhiyun #define DISP_CC_MDSS_BYTE1_CLK 6 17*4882a593Smuzhiyun #define DISP_CC_MDSS_BYTE1_CLK_SRC 7 18*4882a593Smuzhiyun #define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 8 19*4882a593Smuzhiyun #define DISP_CC_MDSS_BYTE1_INTF_CLK 9 20*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_AUX1_CLK 10 21*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_AUX1_CLK_SRC 11 22*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_AUX_CLK 12 23*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_AUX_CLK_SRC 13 24*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_LINK1_CLK 14 25*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_LINK1_CLK_SRC 15 26*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC 16 27*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_LINK1_INTF_CLK 17 28*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_LINK_CLK 18 29*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_LINK_CLK_SRC 19 30*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 20 31*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_LINK_INTF_CLK 21 32*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_PIXEL1_CLK 22 33*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 23 34*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_PIXEL2_CLK 24 35*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC 25 36*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_PIXEL_CLK 26 37*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 27 38*4882a593Smuzhiyun #define DISP_CC_MDSS_ESC0_CLK 28 39*4882a593Smuzhiyun #define DISP_CC_MDSS_ESC0_CLK_SRC 29 40*4882a593Smuzhiyun #define DISP_CC_MDSS_ESC1_CLK 30 41*4882a593Smuzhiyun #define DISP_CC_MDSS_ESC1_CLK_SRC 31 42*4882a593Smuzhiyun #define DISP_CC_MDSS_MDP_CLK 32 43*4882a593Smuzhiyun #define DISP_CC_MDSS_MDP_CLK_SRC 33 44*4882a593Smuzhiyun #define DISP_CC_MDSS_MDP_LUT_CLK 34 45*4882a593Smuzhiyun #define DISP_CC_MDSS_NON_GDSC_AHB_CLK 35 46*4882a593Smuzhiyun #define DISP_CC_MDSS_PCLK0_CLK 36 47*4882a593Smuzhiyun #define DISP_CC_MDSS_PCLK0_CLK_SRC 37 48*4882a593Smuzhiyun #define DISP_CC_MDSS_PCLK1_CLK 38 49*4882a593Smuzhiyun #define DISP_CC_MDSS_PCLK1_CLK_SRC 39 50*4882a593Smuzhiyun #define DISP_CC_MDSS_ROT_CLK 40 51*4882a593Smuzhiyun #define DISP_CC_MDSS_ROT_CLK_SRC 41 52*4882a593Smuzhiyun #define DISP_CC_MDSS_RSCC_AHB_CLK 42 53*4882a593Smuzhiyun #define DISP_CC_MDSS_RSCC_VSYNC_CLK 43 54*4882a593Smuzhiyun #define DISP_CC_MDSS_VSYNC_CLK 44 55*4882a593Smuzhiyun #define DISP_CC_MDSS_VSYNC_CLK_SRC 45 56*4882a593Smuzhiyun #define DISP_CC_PLL0 46 57*4882a593Smuzhiyun #define DISP_CC_PLL1 47 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* DISP_CC Reset */ 60*4882a593Smuzhiyun #define DISP_CC_MDSS_CORE_BCR 0 61*4882a593Smuzhiyun #define DISP_CC_MDSS_RSCC_BCR 1 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* DISP_CC GDSCR */ 64*4882a593Smuzhiyun #define MDSS_GDSC 0 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #endif 67