1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define DISP_CC_PLL0 0 10*4882a593Smuzhiyun #define DISP_CC_PLL0_OUT_EVEN 1 11*4882a593Smuzhiyun #define DISP_CC_MDSS_AHB_CLK 2 12*4882a593Smuzhiyun #define DISP_CC_MDSS_AHB_CLK_SRC 3 13*4882a593Smuzhiyun #define DISP_CC_MDSS_BYTE0_CLK 4 14*4882a593Smuzhiyun #define DISP_CC_MDSS_BYTE0_CLK_SRC 5 15*4882a593Smuzhiyun #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6 16*4882a593Smuzhiyun #define DISP_CC_MDSS_BYTE0_INTF_CLK 7 17*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_AUX_CLK 8 18*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_AUX_CLK_SRC 9 19*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_CRYPTO_CLK 10 20*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 11 21*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_LINK_CLK 12 22*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_LINK_CLK_SRC 13 23*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 14 24*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_LINK_INTF_CLK 15 25*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_PIXEL_CLK 16 26*4882a593Smuzhiyun #define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 17 27*4882a593Smuzhiyun #define DISP_CC_MDSS_ESC0_CLK 18 28*4882a593Smuzhiyun #define DISP_CC_MDSS_ESC0_CLK_SRC 19 29*4882a593Smuzhiyun #define DISP_CC_MDSS_MDP_CLK 20 30*4882a593Smuzhiyun #define DISP_CC_MDSS_MDP_CLK_SRC 21 31*4882a593Smuzhiyun #define DISP_CC_MDSS_MDP_LUT_CLK 22 32*4882a593Smuzhiyun #define DISP_CC_MDSS_NON_GDSC_AHB_CLK 23 33*4882a593Smuzhiyun #define DISP_CC_MDSS_PCLK0_CLK 24 34*4882a593Smuzhiyun #define DISP_CC_MDSS_PCLK0_CLK_SRC 25 35*4882a593Smuzhiyun #define DISP_CC_MDSS_ROT_CLK 26 36*4882a593Smuzhiyun #define DISP_CC_MDSS_ROT_CLK_SRC 27 37*4882a593Smuzhiyun #define DISP_CC_MDSS_RSCC_AHB_CLK 28 38*4882a593Smuzhiyun #define DISP_CC_MDSS_RSCC_VSYNC_CLK 29 39*4882a593Smuzhiyun #define DISP_CC_MDSS_VSYNC_CLK 30 40*4882a593Smuzhiyun #define DISP_CC_MDSS_VSYNC_CLK_SRC 31 41*4882a593Smuzhiyun #define DISP_CC_XO_CLK 32 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* DISP_CC GDSCR */ 44*4882a593Smuzhiyun #define MDSS_GDSC 0 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #endif 47