1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* CAM_CC clock registers */ 10*4882a593Smuzhiyun #define CAM_CC_BPS_AHB_CLK 0 11*4882a593Smuzhiyun #define CAM_CC_BPS_AREG_CLK 1 12*4882a593Smuzhiyun #define CAM_CC_BPS_AXI_CLK 2 13*4882a593Smuzhiyun #define CAM_CC_BPS_CLK 3 14*4882a593Smuzhiyun #define CAM_CC_BPS_CLK_SRC 4 15*4882a593Smuzhiyun #define CAM_CC_CAMNOC_ATB_CLK 5 16*4882a593Smuzhiyun #define CAM_CC_CAMNOC_AXI_CLK 6 17*4882a593Smuzhiyun #define CAM_CC_CCI_CLK 7 18*4882a593Smuzhiyun #define CAM_CC_CCI_CLK_SRC 8 19*4882a593Smuzhiyun #define CAM_CC_CPAS_AHB_CLK 9 20*4882a593Smuzhiyun #define CAM_CC_CPHY_RX_CLK_SRC 10 21*4882a593Smuzhiyun #define CAM_CC_CSI0PHYTIMER_CLK 11 22*4882a593Smuzhiyun #define CAM_CC_CSI0PHYTIMER_CLK_SRC 12 23*4882a593Smuzhiyun #define CAM_CC_CSI1PHYTIMER_CLK 13 24*4882a593Smuzhiyun #define CAM_CC_CSI1PHYTIMER_CLK_SRC 14 25*4882a593Smuzhiyun #define CAM_CC_CSI2PHYTIMER_CLK 15 26*4882a593Smuzhiyun #define CAM_CC_CSI2PHYTIMER_CLK_SRC 16 27*4882a593Smuzhiyun #define CAM_CC_CSI3PHYTIMER_CLK 17 28*4882a593Smuzhiyun #define CAM_CC_CSI3PHYTIMER_CLK_SRC 18 29*4882a593Smuzhiyun #define CAM_CC_CSIPHY0_CLK 19 30*4882a593Smuzhiyun #define CAM_CC_CSIPHY1_CLK 20 31*4882a593Smuzhiyun #define CAM_CC_CSIPHY2_CLK 21 32*4882a593Smuzhiyun #define CAM_CC_CSIPHY3_CLK 22 33*4882a593Smuzhiyun #define CAM_CC_FAST_AHB_CLK_SRC 23 34*4882a593Smuzhiyun #define CAM_CC_FD_CORE_CLK 24 35*4882a593Smuzhiyun #define CAM_CC_FD_CORE_CLK_SRC 25 36*4882a593Smuzhiyun #define CAM_CC_FD_CORE_UAR_CLK 26 37*4882a593Smuzhiyun #define CAM_CC_ICP_APB_CLK 27 38*4882a593Smuzhiyun #define CAM_CC_ICP_ATB_CLK 28 39*4882a593Smuzhiyun #define CAM_CC_ICP_CLK 29 40*4882a593Smuzhiyun #define CAM_CC_ICP_CLK_SRC 30 41*4882a593Smuzhiyun #define CAM_CC_ICP_CTI_CLK 31 42*4882a593Smuzhiyun #define CAM_CC_ICP_TS_CLK 32 43*4882a593Smuzhiyun #define CAM_CC_IFE_0_AXI_CLK 33 44*4882a593Smuzhiyun #define CAM_CC_IFE_0_CLK 34 45*4882a593Smuzhiyun #define CAM_CC_IFE_0_CLK_SRC 35 46*4882a593Smuzhiyun #define CAM_CC_IFE_0_CPHY_RX_CLK 36 47*4882a593Smuzhiyun #define CAM_CC_IFE_0_CSID_CLK 37 48*4882a593Smuzhiyun #define CAM_CC_IFE_0_CSID_CLK_SRC 38 49*4882a593Smuzhiyun #define CAM_CC_IFE_0_DSP_CLK 39 50*4882a593Smuzhiyun #define CAM_CC_IFE_1_AXI_CLK 40 51*4882a593Smuzhiyun #define CAM_CC_IFE_1_CLK 41 52*4882a593Smuzhiyun #define CAM_CC_IFE_1_CLK_SRC 42 53*4882a593Smuzhiyun #define CAM_CC_IFE_1_CPHY_RX_CLK 43 54*4882a593Smuzhiyun #define CAM_CC_IFE_1_CSID_CLK 44 55*4882a593Smuzhiyun #define CAM_CC_IFE_1_CSID_CLK_SRC 45 56*4882a593Smuzhiyun #define CAM_CC_IFE_1_DSP_CLK 46 57*4882a593Smuzhiyun #define CAM_CC_IFE_LITE_CLK 47 58*4882a593Smuzhiyun #define CAM_CC_IFE_LITE_CLK_SRC 48 59*4882a593Smuzhiyun #define CAM_CC_IFE_LITE_CPHY_RX_CLK 49 60*4882a593Smuzhiyun #define CAM_CC_IFE_LITE_CSID_CLK 50 61*4882a593Smuzhiyun #define CAM_CC_IFE_LITE_CSID_CLK_SRC 51 62*4882a593Smuzhiyun #define CAM_CC_IPE_0_AHB_CLK 52 63*4882a593Smuzhiyun #define CAM_CC_IPE_0_AREG_CLK 53 64*4882a593Smuzhiyun #define CAM_CC_IPE_0_AXI_CLK 54 65*4882a593Smuzhiyun #define CAM_CC_IPE_0_CLK 55 66*4882a593Smuzhiyun #define CAM_CC_IPE_0_CLK_SRC 56 67*4882a593Smuzhiyun #define CAM_CC_IPE_1_AHB_CLK 57 68*4882a593Smuzhiyun #define CAM_CC_IPE_1_AREG_CLK 58 69*4882a593Smuzhiyun #define CAM_CC_IPE_1_AXI_CLK 59 70*4882a593Smuzhiyun #define CAM_CC_IPE_1_CLK 60 71*4882a593Smuzhiyun #define CAM_CC_IPE_1_CLK_SRC 61 72*4882a593Smuzhiyun #define CAM_CC_JPEG_CLK 62 73*4882a593Smuzhiyun #define CAM_CC_JPEG_CLK_SRC 63 74*4882a593Smuzhiyun #define CAM_CC_LRME_CLK 64 75*4882a593Smuzhiyun #define CAM_CC_LRME_CLK_SRC 65 76*4882a593Smuzhiyun #define CAM_CC_MCLK0_CLK 66 77*4882a593Smuzhiyun #define CAM_CC_MCLK0_CLK_SRC 67 78*4882a593Smuzhiyun #define CAM_CC_MCLK1_CLK 68 79*4882a593Smuzhiyun #define CAM_CC_MCLK1_CLK_SRC 69 80*4882a593Smuzhiyun #define CAM_CC_MCLK2_CLK 70 81*4882a593Smuzhiyun #define CAM_CC_MCLK2_CLK_SRC 71 82*4882a593Smuzhiyun #define CAM_CC_MCLK3_CLK 72 83*4882a593Smuzhiyun #define CAM_CC_MCLK3_CLK_SRC 73 84*4882a593Smuzhiyun #define CAM_CC_PLL0 74 85*4882a593Smuzhiyun #define CAM_CC_PLL0_OUT_EVEN 75 86*4882a593Smuzhiyun #define CAM_CC_PLL1 76 87*4882a593Smuzhiyun #define CAM_CC_PLL1_OUT_EVEN 77 88*4882a593Smuzhiyun #define CAM_CC_PLL2 78 89*4882a593Smuzhiyun #define CAM_CC_PLL2_OUT_EVEN 79 90*4882a593Smuzhiyun #define CAM_CC_PLL3 80 91*4882a593Smuzhiyun #define CAM_CC_PLL3_OUT_EVEN 81 92*4882a593Smuzhiyun #define CAM_CC_SLOW_AHB_CLK_SRC 82 93*4882a593Smuzhiyun #define CAM_CC_SOC_AHB_CLK 83 94*4882a593Smuzhiyun #define CAM_CC_SYS_TMR_CLK 84 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* CAM_CC Resets */ 97*4882a593Smuzhiyun #define TITAN_CAM_CC_CCI_BCR 0 98*4882a593Smuzhiyun #define TITAN_CAM_CC_CPAS_BCR 1 99*4882a593Smuzhiyun #define TITAN_CAM_CC_CSI0PHY_BCR 2 100*4882a593Smuzhiyun #define TITAN_CAM_CC_CSI1PHY_BCR 3 101*4882a593Smuzhiyun #define TITAN_CAM_CC_CSI2PHY_BCR 4 102*4882a593Smuzhiyun #define TITAN_CAM_CC_MCLK0_BCR 5 103*4882a593Smuzhiyun #define TITAN_CAM_CC_MCLK1_BCR 6 104*4882a593Smuzhiyun #define TITAN_CAM_CC_MCLK2_BCR 7 105*4882a593Smuzhiyun #define TITAN_CAM_CC_MCLK3_BCR 8 106*4882a593Smuzhiyun #define TITAN_CAM_CC_TITAN_TOP_BCR 9 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* CAM_CC GDSCRs */ 109*4882a593Smuzhiyun #define BPS_GDSC 0 110*4882a593Smuzhiyun #define IPE_0_GDSC 1 111*4882a593Smuzhiyun #define IPE_1_GDSC 2 112*4882a593Smuzhiyun #define IFE_0_GDSC 3 113*4882a593Smuzhiyun #define IFE_1_GDSC 4 114*4882a593Smuzhiyun #define TITAN_TOP_GDSC 5 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #endif 117