1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_APQ_MMCC_8084_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_APQ_MMCC_8084_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define MMSS_AHB_CLK_SRC 0 10*4882a593Smuzhiyun #define MMSS_AXI_CLK_SRC 1 11*4882a593Smuzhiyun #define MMPLL0 2 12*4882a593Smuzhiyun #define MMPLL0_VOTE 3 13*4882a593Smuzhiyun #define MMPLL1 4 14*4882a593Smuzhiyun #define MMPLL1_VOTE 5 15*4882a593Smuzhiyun #define MMPLL2 6 16*4882a593Smuzhiyun #define MMPLL3 7 17*4882a593Smuzhiyun #define MMPLL4 8 18*4882a593Smuzhiyun #define CSI0_CLK_SRC 9 19*4882a593Smuzhiyun #define CSI1_CLK_SRC 10 20*4882a593Smuzhiyun #define CSI2_CLK_SRC 11 21*4882a593Smuzhiyun #define CSI3_CLK_SRC 12 22*4882a593Smuzhiyun #define VCODEC0_CLK_SRC 13 23*4882a593Smuzhiyun #define VFE0_CLK_SRC 14 24*4882a593Smuzhiyun #define VFE1_CLK_SRC 15 25*4882a593Smuzhiyun #define MDP_CLK_SRC 16 26*4882a593Smuzhiyun #define PCLK0_CLK_SRC 17 27*4882a593Smuzhiyun #define PCLK1_CLK_SRC 18 28*4882a593Smuzhiyun #define OCMEMNOC_CLK_SRC 19 29*4882a593Smuzhiyun #define GFX3D_CLK_SRC 20 30*4882a593Smuzhiyun #define JPEG0_CLK_SRC 21 31*4882a593Smuzhiyun #define JPEG1_CLK_SRC 22 32*4882a593Smuzhiyun #define JPEG2_CLK_SRC 23 33*4882a593Smuzhiyun #define EDPPIXEL_CLK_SRC 24 34*4882a593Smuzhiyun #define EXTPCLK_CLK_SRC 25 35*4882a593Smuzhiyun #define VP_CLK_SRC 26 36*4882a593Smuzhiyun #define CCI_CLK_SRC 27 37*4882a593Smuzhiyun #define CAMSS_GP0_CLK_SRC 28 38*4882a593Smuzhiyun #define CAMSS_GP1_CLK_SRC 29 39*4882a593Smuzhiyun #define MCLK0_CLK_SRC 30 40*4882a593Smuzhiyun #define MCLK1_CLK_SRC 31 41*4882a593Smuzhiyun #define MCLK2_CLK_SRC 32 42*4882a593Smuzhiyun #define MCLK3_CLK_SRC 33 43*4882a593Smuzhiyun #define CSI0PHYTIMER_CLK_SRC 34 44*4882a593Smuzhiyun #define CSI1PHYTIMER_CLK_SRC 35 45*4882a593Smuzhiyun #define CSI2PHYTIMER_CLK_SRC 36 46*4882a593Smuzhiyun #define CPP_CLK_SRC 37 47*4882a593Smuzhiyun #define BYTE0_CLK_SRC 38 48*4882a593Smuzhiyun #define BYTE1_CLK_SRC 39 49*4882a593Smuzhiyun #define EDPAUX_CLK_SRC 40 50*4882a593Smuzhiyun #define EDPLINK_CLK_SRC 41 51*4882a593Smuzhiyun #define ESC0_CLK_SRC 42 52*4882a593Smuzhiyun #define ESC1_CLK_SRC 43 53*4882a593Smuzhiyun #define HDMI_CLK_SRC 44 54*4882a593Smuzhiyun #define VSYNC_CLK_SRC 45 55*4882a593Smuzhiyun #define MMSS_RBCPR_CLK_SRC 46 56*4882a593Smuzhiyun #define RBBMTIMER_CLK_SRC 47 57*4882a593Smuzhiyun #define MAPLE_CLK_SRC 48 58*4882a593Smuzhiyun #define VDP_CLK_SRC 49 59*4882a593Smuzhiyun #define VPU_BUS_CLK_SRC 50 60*4882a593Smuzhiyun #define MMSS_CXO_CLK 51 61*4882a593Smuzhiyun #define MMSS_SLEEPCLK_CLK 52 62*4882a593Smuzhiyun #define AVSYNC_AHB_CLK 53 63*4882a593Smuzhiyun #define AVSYNC_EDPPIXEL_CLK 54 64*4882a593Smuzhiyun #define AVSYNC_EXTPCLK_CLK 55 65*4882a593Smuzhiyun #define AVSYNC_PCLK0_CLK 56 66*4882a593Smuzhiyun #define AVSYNC_PCLK1_CLK 57 67*4882a593Smuzhiyun #define AVSYNC_VP_CLK 58 68*4882a593Smuzhiyun #define CAMSS_AHB_CLK 59 69*4882a593Smuzhiyun #define CAMSS_CCI_CCI_AHB_CLK 60 70*4882a593Smuzhiyun #define CAMSS_CCI_CCI_CLK 61 71*4882a593Smuzhiyun #define CAMSS_CSI0_AHB_CLK 62 72*4882a593Smuzhiyun #define CAMSS_CSI0_CLK 63 73*4882a593Smuzhiyun #define CAMSS_CSI0PHY_CLK 64 74*4882a593Smuzhiyun #define CAMSS_CSI0PIX_CLK 65 75*4882a593Smuzhiyun #define CAMSS_CSI0RDI_CLK 66 76*4882a593Smuzhiyun #define CAMSS_CSI1_AHB_CLK 67 77*4882a593Smuzhiyun #define CAMSS_CSI1_CLK 68 78*4882a593Smuzhiyun #define CAMSS_CSI1PHY_CLK 69 79*4882a593Smuzhiyun #define CAMSS_CSI1PIX_CLK 70 80*4882a593Smuzhiyun #define CAMSS_CSI1RDI_CLK 71 81*4882a593Smuzhiyun #define CAMSS_CSI2_AHB_CLK 72 82*4882a593Smuzhiyun #define CAMSS_CSI2_CLK 73 83*4882a593Smuzhiyun #define CAMSS_CSI2PHY_CLK 74 84*4882a593Smuzhiyun #define CAMSS_CSI2PIX_CLK 75 85*4882a593Smuzhiyun #define CAMSS_CSI2RDI_CLK 76 86*4882a593Smuzhiyun #define CAMSS_CSI3_AHB_CLK 77 87*4882a593Smuzhiyun #define CAMSS_CSI3_CLK 78 88*4882a593Smuzhiyun #define CAMSS_CSI3PHY_CLK 79 89*4882a593Smuzhiyun #define CAMSS_CSI3PIX_CLK 80 90*4882a593Smuzhiyun #define CAMSS_CSI3RDI_CLK 81 91*4882a593Smuzhiyun #define CAMSS_CSI_VFE0_CLK 82 92*4882a593Smuzhiyun #define CAMSS_CSI_VFE1_CLK 83 93*4882a593Smuzhiyun #define CAMSS_GP0_CLK 84 94*4882a593Smuzhiyun #define CAMSS_GP1_CLK 85 95*4882a593Smuzhiyun #define CAMSS_ISPIF_AHB_CLK 86 96*4882a593Smuzhiyun #define CAMSS_JPEG_JPEG0_CLK 87 97*4882a593Smuzhiyun #define CAMSS_JPEG_JPEG1_CLK 88 98*4882a593Smuzhiyun #define CAMSS_JPEG_JPEG2_CLK 89 99*4882a593Smuzhiyun #define CAMSS_JPEG_JPEG_AHB_CLK 90 100*4882a593Smuzhiyun #define CAMSS_JPEG_JPEG_AXI_CLK 91 101*4882a593Smuzhiyun #define CAMSS_MCLK0_CLK 92 102*4882a593Smuzhiyun #define CAMSS_MCLK1_CLK 93 103*4882a593Smuzhiyun #define CAMSS_MCLK2_CLK 94 104*4882a593Smuzhiyun #define CAMSS_MCLK3_CLK 95 105*4882a593Smuzhiyun #define CAMSS_MICRO_AHB_CLK 96 106*4882a593Smuzhiyun #define CAMSS_PHY0_CSI0PHYTIMER_CLK 97 107*4882a593Smuzhiyun #define CAMSS_PHY1_CSI1PHYTIMER_CLK 98 108*4882a593Smuzhiyun #define CAMSS_PHY2_CSI2PHYTIMER_CLK 99 109*4882a593Smuzhiyun #define CAMSS_TOP_AHB_CLK 100 110*4882a593Smuzhiyun #define CAMSS_VFE_CPP_AHB_CLK 101 111*4882a593Smuzhiyun #define CAMSS_VFE_CPP_CLK 102 112*4882a593Smuzhiyun #define CAMSS_VFE_VFE0_CLK 103 113*4882a593Smuzhiyun #define CAMSS_VFE_VFE1_CLK 104 114*4882a593Smuzhiyun #define CAMSS_VFE_VFE_AHB_CLK 105 115*4882a593Smuzhiyun #define CAMSS_VFE_VFE_AXI_CLK 106 116*4882a593Smuzhiyun #define MDSS_AHB_CLK 107 117*4882a593Smuzhiyun #define MDSS_AXI_CLK 108 118*4882a593Smuzhiyun #define MDSS_BYTE0_CLK 109 119*4882a593Smuzhiyun #define MDSS_BYTE1_CLK 110 120*4882a593Smuzhiyun #define MDSS_EDPAUX_CLK 111 121*4882a593Smuzhiyun #define MDSS_EDPLINK_CLK 112 122*4882a593Smuzhiyun #define MDSS_EDPPIXEL_CLK 113 123*4882a593Smuzhiyun #define MDSS_ESC0_CLK 114 124*4882a593Smuzhiyun #define MDSS_ESC1_CLK 115 125*4882a593Smuzhiyun #define MDSS_EXTPCLK_CLK 116 126*4882a593Smuzhiyun #define MDSS_HDMI_AHB_CLK 117 127*4882a593Smuzhiyun #define MDSS_HDMI_CLK 118 128*4882a593Smuzhiyun #define MDSS_MDP_CLK 119 129*4882a593Smuzhiyun #define MDSS_MDP_LUT_CLK 120 130*4882a593Smuzhiyun #define MDSS_PCLK0_CLK 121 131*4882a593Smuzhiyun #define MDSS_PCLK1_CLK 122 132*4882a593Smuzhiyun #define MDSS_VSYNC_CLK 123 133*4882a593Smuzhiyun #define MMSS_RBCPR_AHB_CLK 124 134*4882a593Smuzhiyun #define MMSS_RBCPR_CLK 125 135*4882a593Smuzhiyun #define MMSS_SPDM_AHB_CLK 126 136*4882a593Smuzhiyun #define MMSS_SPDM_AXI_CLK 127 137*4882a593Smuzhiyun #define MMSS_SPDM_CSI0_CLK 128 138*4882a593Smuzhiyun #define MMSS_SPDM_GFX3D_CLK 129 139*4882a593Smuzhiyun #define MMSS_SPDM_JPEG0_CLK 130 140*4882a593Smuzhiyun #define MMSS_SPDM_JPEG1_CLK 131 141*4882a593Smuzhiyun #define MMSS_SPDM_JPEG2_CLK 132 142*4882a593Smuzhiyun #define MMSS_SPDM_MDP_CLK 133 143*4882a593Smuzhiyun #define MMSS_SPDM_PCLK0_CLK 134 144*4882a593Smuzhiyun #define MMSS_SPDM_PCLK1_CLK 135 145*4882a593Smuzhiyun #define MMSS_SPDM_VCODEC0_CLK 136 146*4882a593Smuzhiyun #define MMSS_SPDM_VFE0_CLK 137 147*4882a593Smuzhiyun #define MMSS_SPDM_VFE1_CLK 138 148*4882a593Smuzhiyun #define MMSS_SPDM_RM_AXI_CLK 139 149*4882a593Smuzhiyun #define MMSS_SPDM_RM_OCMEMNOC_CLK 140 150*4882a593Smuzhiyun #define MMSS_MISC_AHB_CLK 141 151*4882a593Smuzhiyun #define MMSS_MMSSNOC_AHB_CLK 142 152*4882a593Smuzhiyun #define MMSS_MMSSNOC_BTO_AHB_CLK 143 153*4882a593Smuzhiyun #define MMSS_MMSSNOC_AXI_CLK 144 154*4882a593Smuzhiyun #define MMSS_S0_AXI_CLK 145 155*4882a593Smuzhiyun #define OCMEMCX_AHB_CLK 146 156*4882a593Smuzhiyun #define OCMEMCX_OCMEMNOC_CLK 147 157*4882a593Smuzhiyun #define OXILI_OCMEMGX_CLK 148 158*4882a593Smuzhiyun #define OXILI_GFX3D_CLK 149 159*4882a593Smuzhiyun #define OXILI_RBBMTIMER_CLK 150 160*4882a593Smuzhiyun #define OXILICX_AHB_CLK 151 161*4882a593Smuzhiyun #define VENUS0_AHB_CLK 152 162*4882a593Smuzhiyun #define VENUS0_AXI_CLK 153 163*4882a593Smuzhiyun #define VENUS0_CORE0_VCODEC_CLK 154 164*4882a593Smuzhiyun #define VENUS0_CORE1_VCODEC_CLK 155 165*4882a593Smuzhiyun #define VENUS0_OCMEMNOC_CLK 156 166*4882a593Smuzhiyun #define VENUS0_VCODEC0_CLK 157 167*4882a593Smuzhiyun #define VPU_AHB_CLK 158 168*4882a593Smuzhiyun #define VPU_AXI_CLK 159 169*4882a593Smuzhiyun #define VPU_BUS_CLK 160 170*4882a593Smuzhiyun #define VPU_CXO_CLK 161 171*4882a593Smuzhiyun #define VPU_MAPLE_CLK 162 172*4882a593Smuzhiyun #define VPU_SLEEP_CLK 163 173*4882a593Smuzhiyun #define VPU_VDP_CLK 164 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* GDSCs */ 176*4882a593Smuzhiyun #define VENUS0_GDSC 0 177*4882a593Smuzhiyun #define VENUS0_CORE0_GDSC 1 178*4882a593Smuzhiyun #define VENUS0_CORE1_GDSC 2 179*4882a593Smuzhiyun #define MDSS_GDSC 3 180*4882a593Smuzhiyun #define CAMSS_JPEG_GDSC 4 181*4882a593Smuzhiyun #define CAMSS_VFE_GDSC 5 182*4882a593Smuzhiyun #define OXILI_GDSC 6 183*4882a593Smuzhiyun #define OXILICX_GDSC 7 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun #endif 186