1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun * Copyright (c) 2018, Craig Tatlor. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MSM_GCC_660_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define BLSP1_QUP1_I2C_APPS_CLK_SRC 0 11*4882a593Smuzhiyun #define BLSP1_QUP1_SPI_APPS_CLK_SRC 1 12*4882a593Smuzhiyun #define BLSP1_QUP2_I2C_APPS_CLK_SRC 2 13*4882a593Smuzhiyun #define BLSP1_QUP2_SPI_APPS_CLK_SRC 3 14*4882a593Smuzhiyun #define BLSP1_QUP3_I2C_APPS_CLK_SRC 4 15*4882a593Smuzhiyun #define BLSP1_QUP3_SPI_APPS_CLK_SRC 5 16*4882a593Smuzhiyun #define BLSP1_QUP4_I2C_APPS_CLK_SRC 6 17*4882a593Smuzhiyun #define BLSP1_QUP4_SPI_APPS_CLK_SRC 7 18*4882a593Smuzhiyun #define BLSP1_UART1_APPS_CLK_SRC 8 19*4882a593Smuzhiyun #define BLSP1_UART2_APPS_CLK_SRC 9 20*4882a593Smuzhiyun #define BLSP2_QUP1_I2C_APPS_CLK_SRC 10 21*4882a593Smuzhiyun #define BLSP2_QUP1_SPI_APPS_CLK_SRC 11 22*4882a593Smuzhiyun #define BLSP2_QUP2_I2C_APPS_CLK_SRC 12 23*4882a593Smuzhiyun #define BLSP2_QUP2_SPI_APPS_CLK_SRC 13 24*4882a593Smuzhiyun #define BLSP2_QUP3_I2C_APPS_CLK_SRC 14 25*4882a593Smuzhiyun #define BLSP2_QUP3_SPI_APPS_CLK_SRC 15 26*4882a593Smuzhiyun #define BLSP2_QUP4_I2C_APPS_CLK_SRC 16 27*4882a593Smuzhiyun #define BLSP2_QUP4_SPI_APPS_CLK_SRC 17 28*4882a593Smuzhiyun #define BLSP2_UART1_APPS_CLK_SRC 18 29*4882a593Smuzhiyun #define BLSP2_UART2_APPS_CLK_SRC 19 30*4882a593Smuzhiyun #define GCC_AGGRE2_UFS_AXI_CLK 20 31*4882a593Smuzhiyun #define GCC_AGGRE2_USB3_AXI_CLK 21 32*4882a593Smuzhiyun #define GCC_BIMC_GFX_CLK 22 33*4882a593Smuzhiyun #define GCC_BIMC_HMSS_AXI_CLK 23 34*4882a593Smuzhiyun #define GCC_BIMC_MSS_Q6_AXI_CLK 24 35*4882a593Smuzhiyun #define GCC_BLSP1_AHB_CLK 25 36*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_I2C_APPS_CLK 26 37*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_SPI_APPS_CLK 27 38*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_I2C_APPS_CLK 28 39*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_SPI_APPS_CLK 29 40*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_I2C_APPS_CLK 30 41*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_SPI_APPS_CLK 31 42*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_I2C_APPS_CLK 32 43*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_SPI_APPS_CLK 33 44*4882a593Smuzhiyun #define GCC_BLSP1_UART1_APPS_CLK 34 45*4882a593Smuzhiyun #define GCC_BLSP1_UART2_APPS_CLK 35 46*4882a593Smuzhiyun #define GCC_BLSP2_AHB_CLK 36 47*4882a593Smuzhiyun #define GCC_BLSP2_QUP1_I2C_APPS_CLK 37 48*4882a593Smuzhiyun #define GCC_BLSP2_QUP1_SPI_APPS_CLK 38 49*4882a593Smuzhiyun #define GCC_BLSP2_QUP2_I2C_APPS_CLK 39 50*4882a593Smuzhiyun #define GCC_BLSP2_QUP2_SPI_APPS_CLK 40 51*4882a593Smuzhiyun #define GCC_BLSP2_QUP3_I2C_APPS_CLK 41 52*4882a593Smuzhiyun #define GCC_BLSP2_QUP3_SPI_APPS_CLK 42 53*4882a593Smuzhiyun #define GCC_BLSP2_QUP4_I2C_APPS_CLK 43 54*4882a593Smuzhiyun #define GCC_BLSP2_QUP4_SPI_APPS_CLK 44 55*4882a593Smuzhiyun #define GCC_BLSP2_UART1_APPS_CLK 45 56*4882a593Smuzhiyun #define GCC_BLSP2_UART2_APPS_CLK 46 57*4882a593Smuzhiyun #define GCC_BOOT_ROM_AHB_CLK 47 58*4882a593Smuzhiyun #define GCC_CFG_NOC_USB2_AXI_CLK 48 59*4882a593Smuzhiyun #define GCC_CFG_NOC_USB3_AXI_CLK 49 60*4882a593Smuzhiyun #define GCC_DCC_AHB_CLK 50 61*4882a593Smuzhiyun #define GCC_GP1_CLK 51 62*4882a593Smuzhiyun #define GCC_GP2_CLK 52 63*4882a593Smuzhiyun #define GCC_GP3_CLK 53 64*4882a593Smuzhiyun #define GCC_GPU_BIMC_GFX_CLK 54 65*4882a593Smuzhiyun #define GCC_GPU_CFG_AHB_CLK 55 66*4882a593Smuzhiyun #define GCC_GPU_GPLL0_CLK 56 67*4882a593Smuzhiyun #define GCC_GPU_GPLL0_DIV_CLK 57 68*4882a593Smuzhiyun #define GCC_HMSS_DVM_BUS_CLK 58 69*4882a593Smuzhiyun #define GCC_HMSS_RBCPR_CLK 59 70*4882a593Smuzhiyun #define GCC_MMSS_GPLL0_CLK 60 71*4882a593Smuzhiyun #define GCC_MMSS_GPLL0_DIV_CLK 61 72*4882a593Smuzhiyun #define GCC_MMSS_NOC_CFG_AHB_CLK 62 73*4882a593Smuzhiyun #define GCC_MMSS_SYS_NOC_AXI_CLK 63 74*4882a593Smuzhiyun #define GCC_MSS_CFG_AHB_CLK 64 75*4882a593Smuzhiyun #define GCC_MSS_GPLL0_DIV_CLK 65 76*4882a593Smuzhiyun #define GCC_MSS_MNOC_BIMC_AXI_CLK 66 77*4882a593Smuzhiyun #define GCC_MSS_Q6_BIMC_AXI_CLK 67 78*4882a593Smuzhiyun #define GCC_MSS_SNOC_AXI_CLK 68 79*4882a593Smuzhiyun #define GCC_PDM2_CLK 69 80*4882a593Smuzhiyun #define GCC_PDM_AHB_CLK 70 81*4882a593Smuzhiyun #define GCC_PRNG_AHB_CLK 71 82*4882a593Smuzhiyun #define GCC_QSPI_AHB_CLK 72 83*4882a593Smuzhiyun #define GCC_QSPI_SER_CLK 73 84*4882a593Smuzhiyun #define GCC_SDCC1_AHB_CLK 74 85*4882a593Smuzhiyun #define GCC_SDCC1_APPS_CLK 75 86*4882a593Smuzhiyun #define GCC_SDCC1_ICE_CORE_CLK 76 87*4882a593Smuzhiyun #define GCC_SDCC2_AHB_CLK 77 88*4882a593Smuzhiyun #define GCC_SDCC2_APPS_CLK 78 89*4882a593Smuzhiyun #define GCC_UFS_AHB_CLK 79 90*4882a593Smuzhiyun #define GCC_UFS_AXI_CLK 80 91*4882a593Smuzhiyun #define GCC_UFS_CLKREF_CLK 81 92*4882a593Smuzhiyun #define GCC_UFS_ICE_CORE_CLK 82 93*4882a593Smuzhiyun #define GCC_UFS_PHY_AUX_CLK 83 94*4882a593Smuzhiyun #define GCC_UFS_RX_SYMBOL_0_CLK 84 95*4882a593Smuzhiyun #define GCC_UFS_RX_SYMBOL_1_CLK 85 96*4882a593Smuzhiyun #define GCC_UFS_TX_SYMBOL_0_CLK 86 97*4882a593Smuzhiyun #define GCC_UFS_UNIPRO_CORE_CLK 87 98*4882a593Smuzhiyun #define GCC_USB20_MASTER_CLK 88 99*4882a593Smuzhiyun #define GCC_USB20_MOCK_UTMI_CLK 89 100*4882a593Smuzhiyun #define GCC_USB20_SLEEP_CLK 90 101*4882a593Smuzhiyun #define GCC_USB30_MASTER_CLK 91 102*4882a593Smuzhiyun #define GCC_USB30_MOCK_UTMI_CLK 92 103*4882a593Smuzhiyun #define GCC_USB30_SLEEP_CLK 93 104*4882a593Smuzhiyun #define GCC_USB3_CLKREF_CLK 94 105*4882a593Smuzhiyun #define GCC_USB3_PHY_AUX_CLK 95 106*4882a593Smuzhiyun #define GCC_USB3_PHY_PIPE_CLK 96 107*4882a593Smuzhiyun #define GCC_USB_PHY_CFG_AHB2PHY_CLK 97 108*4882a593Smuzhiyun #define GP1_CLK_SRC 98 109*4882a593Smuzhiyun #define GP2_CLK_SRC 99 110*4882a593Smuzhiyun #define GP3_CLK_SRC 100 111*4882a593Smuzhiyun #define GPLL0 101 112*4882a593Smuzhiyun #define GPLL0_EARLY 102 113*4882a593Smuzhiyun #define GPLL1 103 114*4882a593Smuzhiyun #define GPLL1_EARLY 104 115*4882a593Smuzhiyun #define GPLL4 105 116*4882a593Smuzhiyun #define GPLL4_EARLY 106 117*4882a593Smuzhiyun #define HMSS_GPLL0_CLK_SRC 107 118*4882a593Smuzhiyun #define HMSS_GPLL4_CLK_SRC 108 119*4882a593Smuzhiyun #define HMSS_RBCPR_CLK_SRC 109 120*4882a593Smuzhiyun #define PDM2_CLK_SRC 110 121*4882a593Smuzhiyun #define QSPI_SER_CLK_SRC 111 122*4882a593Smuzhiyun #define SDCC1_APPS_CLK_SRC 112 123*4882a593Smuzhiyun #define SDCC1_ICE_CORE_CLK_SRC 113 124*4882a593Smuzhiyun #define SDCC2_APPS_CLK_SRC 114 125*4882a593Smuzhiyun #define UFS_AXI_CLK_SRC 115 126*4882a593Smuzhiyun #define UFS_ICE_CORE_CLK_SRC 116 127*4882a593Smuzhiyun #define UFS_PHY_AUX_CLK_SRC 117 128*4882a593Smuzhiyun #define UFS_UNIPRO_CORE_CLK_SRC 118 129*4882a593Smuzhiyun #define USB20_MASTER_CLK_SRC 119 130*4882a593Smuzhiyun #define USB20_MOCK_UTMI_CLK_SRC 120 131*4882a593Smuzhiyun #define USB30_MASTER_CLK_SRC 121 132*4882a593Smuzhiyun #define USB30_MOCK_UTMI_CLK_SRC 122 133*4882a593Smuzhiyun #define USB3_PHY_AUX_CLK_SRC 123 134*4882a593Smuzhiyun #define GPLL0_OUT_MSSCC 124 135*4882a593Smuzhiyun #define GCC_UFS_AXI_HW_CTL_CLK 125 136*4882a593Smuzhiyun #define GCC_UFS_ICE_CORE_HW_CTL_CLK 126 137*4882a593Smuzhiyun #define GCC_UFS_PHY_AUX_HW_CTL_CLK 127 138*4882a593Smuzhiyun #define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 128 139*4882a593Smuzhiyun #define GCC_RX0_USB2_CLKREF_CLK 129 140*4882a593Smuzhiyun #define GCC_RX1_USB2_CLKREF_CLK 130 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #define PCIE_0_GDSC 0 143*4882a593Smuzhiyun #define UFS_GDSC 1 144*4882a593Smuzhiyun #define USB_30_GDSC 2 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define GCC_QUSB2PHY_PRIM_BCR 0 147*4882a593Smuzhiyun #define GCC_QUSB2PHY_SEC_BCR 1 148*4882a593Smuzhiyun #define GCC_UFS_BCR 2 149*4882a593Smuzhiyun #define GCC_USB3_DP_PHY_BCR 3 150*4882a593Smuzhiyun #define GCC_USB3_PHY_BCR 4 151*4882a593Smuzhiyun #define GCC_USB3PHY_PHY_BCR 5 152*4882a593Smuzhiyun #define GCC_USB_20_BCR 6 153*4882a593Smuzhiyun #define GCC_USB_30_BCR 7 154*4882a593Smuzhiyun #define GCC_USB_PHY_CFG_AHB2PHY_BCR 8 155*4882a593Smuzhiyun #define GCC_MSS_RESTART 9 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #endif 158