xref: /OK3568_Linux_fs/kernel/include/dt-bindings/clock/qcom,gcc-msm8998.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2016, The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #define BLSP1_QUP1_I2C_APPS_CLK_SRC				0
10*4882a593Smuzhiyun #define BLSP1_QUP1_SPI_APPS_CLK_SRC				1
11*4882a593Smuzhiyun #define BLSP1_QUP2_I2C_APPS_CLK_SRC				2
12*4882a593Smuzhiyun #define BLSP1_QUP2_SPI_APPS_CLK_SRC				3
13*4882a593Smuzhiyun #define BLSP1_QUP3_I2C_APPS_CLK_SRC				4
14*4882a593Smuzhiyun #define BLSP1_QUP3_SPI_APPS_CLK_SRC				5
15*4882a593Smuzhiyun #define BLSP1_QUP4_I2C_APPS_CLK_SRC				6
16*4882a593Smuzhiyun #define BLSP1_QUP4_SPI_APPS_CLK_SRC				7
17*4882a593Smuzhiyun #define BLSP1_QUP5_I2C_APPS_CLK_SRC				8
18*4882a593Smuzhiyun #define BLSP1_QUP5_SPI_APPS_CLK_SRC				9
19*4882a593Smuzhiyun #define BLSP1_QUP6_I2C_APPS_CLK_SRC				10
20*4882a593Smuzhiyun #define BLSP1_QUP6_SPI_APPS_CLK_SRC				11
21*4882a593Smuzhiyun #define BLSP1_UART1_APPS_CLK_SRC				12
22*4882a593Smuzhiyun #define BLSP1_UART2_APPS_CLK_SRC				13
23*4882a593Smuzhiyun #define BLSP1_UART3_APPS_CLK_SRC				14
24*4882a593Smuzhiyun #define BLSP2_QUP1_I2C_APPS_CLK_SRC				15
25*4882a593Smuzhiyun #define BLSP2_QUP1_SPI_APPS_CLK_SRC				16
26*4882a593Smuzhiyun #define BLSP2_QUP2_I2C_APPS_CLK_SRC				17
27*4882a593Smuzhiyun #define BLSP2_QUP2_SPI_APPS_CLK_SRC				18
28*4882a593Smuzhiyun #define BLSP2_QUP3_I2C_APPS_CLK_SRC				19
29*4882a593Smuzhiyun #define BLSP2_QUP3_SPI_APPS_CLK_SRC				20
30*4882a593Smuzhiyun #define BLSP2_QUP4_I2C_APPS_CLK_SRC				21
31*4882a593Smuzhiyun #define BLSP2_QUP4_SPI_APPS_CLK_SRC				22
32*4882a593Smuzhiyun #define BLSP2_QUP5_I2C_APPS_CLK_SRC				23
33*4882a593Smuzhiyun #define BLSP2_QUP5_SPI_APPS_CLK_SRC				24
34*4882a593Smuzhiyun #define BLSP2_QUP6_I2C_APPS_CLK_SRC				25
35*4882a593Smuzhiyun #define BLSP2_QUP6_SPI_APPS_CLK_SRC				26
36*4882a593Smuzhiyun #define BLSP2_UART1_APPS_CLK_SRC				27
37*4882a593Smuzhiyun #define BLSP2_UART2_APPS_CLK_SRC				28
38*4882a593Smuzhiyun #define BLSP2_UART3_APPS_CLK_SRC				29
39*4882a593Smuzhiyun #define GCC_AGGRE1_NOC_XO_CLK					30
40*4882a593Smuzhiyun #define GCC_AGGRE1_UFS_AXI_CLK					31
41*4882a593Smuzhiyun #define GCC_AGGRE1_USB3_AXI_CLK					32
42*4882a593Smuzhiyun #define GCC_APSS_QDSS_TSCTR_DIV2_CLK				33
43*4882a593Smuzhiyun #define GCC_APSS_QDSS_TSCTR_DIV8_CLK				34
44*4882a593Smuzhiyun #define GCC_BIMC_HMSS_AXI_CLK					35
45*4882a593Smuzhiyun #define GCC_BIMC_MSS_Q6_AXI_CLK					36
46*4882a593Smuzhiyun #define GCC_BLSP1_AHB_CLK					37
47*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_I2C_APPS_CLK				38
48*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_SPI_APPS_CLK				39
49*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_I2C_APPS_CLK				40
50*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_SPI_APPS_CLK				41
51*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_I2C_APPS_CLK				42
52*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_SPI_APPS_CLK				43
53*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_I2C_APPS_CLK				44
54*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_SPI_APPS_CLK				45
55*4882a593Smuzhiyun #define GCC_BLSP1_QUP5_I2C_APPS_CLK				46
56*4882a593Smuzhiyun #define GCC_BLSP1_QUP5_SPI_APPS_CLK				47
57*4882a593Smuzhiyun #define GCC_BLSP1_QUP6_I2C_APPS_CLK				48
58*4882a593Smuzhiyun #define GCC_BLSP1_QUP6_SPI_APPS_CLK				49
59*4882a593Smuzhiyun #define GCC_BLSP1_SLEEP_CLK					50
60*4882a593Smuzhiyun #define GCC_BLSP1_UART1_APPS_CLK				51
61*4882a593Smuzhiyun #define GCC_BLSP1_UART2_APPS_CLK				52
62*4882a593Smuzhiyun #define GCC_BLSP1_UART3_APPS_CLK				53
63*4882a593Smuzhiyun #define GCC_BLSP2_AHB_CLK					54
64*4882a593Smuzhiyun #define GCC_BLSP2_QUP1_I2C_APPS_CLK				55
65*4882a593Smuzhiyun #define GCC_BLSP2_QUP1_SPI_APPS_CLK				56
66*4882a593Smuzhiyun #define GCC_BLSP2_QUP2_I2C_APPS_CLK				57
67*4882a593Smuzhiyun #define GCC_BLSP2_QUP2_SPI_APPS_CLK				58
68*4882a593Smuzhiyun #define GCC_BLSP2_QUP3_I2C_APPS_CLK				59
69*4882a593Smuzhiyun #define GCC_BLSP2_QUP3_SPI_APPS_CLK				60
70*4882a593Smuzhiyun #define GCC_BLSP2_QUP4_I2C_APPS_CLK				61
71*4882a593Smuzhiyun #define GCC_BLSP2_QUP4_SPI_APPS_CLK				62
72*4882a593Smuzhiyun #define GCC_BLSP2_QUP5_I2C_APPS_CLK				63
73*4882a593Smuzhiyun #define GCC_BLSP2_QUP5_SPI_APPS_CLK				64
74*4882a593Smuzhiyun #define GCC_BLSP2_QUP6_I2C_APPS_CLK				65
75*4882a593Smuzhiyun #define GCC_BLSP2_QUP6_SPI_APPS_CLK				66
76*4882a593Smuzhiyun #define GCC_BLSP2_SLEEP_CLK					67
77*4882a593Smuzhiyun #define GCC_BLSP2_UART1_APPS_CLK				68
78*4882a593Smuzhiyun #define GCC_BLSP2_UART2_APPS_CLK				69
79*4882a593Smuzhiyun #define GCC_BLSP2_UART3_APPS_CLK				70
80*4882a593Smuzhiyun #define GCC_CFG_NOC_USB3_AXI_CLK				71
81*4882a593Smuzhiyun #define GCC_GP1_CLK						72
82*4882a593Smuzhiyun #define GCC_GP2_CLK						73
83*4882a593Smuzhiyun #define GCC_GP3_CLK						74
84*4882a593Smuzhiyun #define GCC_GPU_BIMC_GFX_CLK					75
85*4882a593Smuzhiyun #define GCC_GPU_BIMC_GFX_SRC_CLK				76
86*4882a593Smuzhiyun #define GCC_GPU_CFG_AHB_CLK					77
87*4882a593Smuzhiyun #define GCC_GPU_SNOC_DVM_GFX_CLK				78
88*4882a593Smuzhiyun #define GCC_HMSS_AHB_CLK					79
89*4882a593Smuzhiyun #define GCC_HMSS_AT_CLK						80
90*4882a593Smuzhiyun #define GCC_HMSS_DVM_BUS_CLK					81
91*4882a593Smuzhiyun #define GCC_HMSS_RBCPR_CLK					82
92*4882a593Smuzhiyun #define GCC_HMSS_TRIG_CLK					83
93*4882a593Smuzhiyun #define GCC_LPASS_AT_CLK					84
94*4882a593Smuzhiyun #define GCC_LPASS_TRIG_CLK					85
95*4882a593Smuzhiyun #define GCC_MMSS_NOC_CFG_AHB_CLK				86
96*4882a593Smuzhiyun #define GCC_MMSS_QM_AHB_CLK					87
97*4882a593Smuzhiyun #define GCC_MMSS_QM_CORE_CLK					88
98*4882a593Smuzhiyun #define GCC_MMSS_SYS_NOC_AXI_CLK				89
99*4882a593Smuzhiyun #define GCC_MSS_AT_CLK						90
100*4882a593Smuzhiyun #define GCC_PCIE_0_AUX_CLK					91
101*4882a593Smuzhiyun #define GCC_PCIE_0_CFG_AHB_CLK					92
102*4882a593Smuzhiyun #define GCC_PCIE_0_MSTR_AXI_CLK					93
103*4882a593Smuzhiyun #define GCC_PCIE_0_PIPE_CLK					94
104*4882a593Smuzhiyun #define GCC_PCIE_0_SLV_AXI_CLK					95
105*4882a593Smuzhiyun #define GCC_PCIE_PHY_AUX_CLK					96
106*4882a593Smuzhiyun #define GCC_PDM2_CLK						97
107*4882a593Smuzhiyun #define GCC_PDM_AHB_CLK						98
108*4882a593Smuzhiyun #define GCC_PDM_XO4_CLK						99
109*4882a593Smuzhiyun #define GCC_PRNG_AHB_CLK					100
110*4882a593Smuzhiyun #define GCC_SDCC2_AHB_CLK					101
111*4882a593Smuzhiyun #define GCC_SDCC2_APPS_CLK					102
112*4882a593Smuzhiyun #define GCC_SDCC4_AHB_CLK					103
113*4882a593Smuzhiyun #define GCC_SDCC4_APPS_CLK					104
114*4882a593Smuzhiyun #define GCC_TSIF_AHB_CLK					105
115*4882a593Smuzhiyun #define GCC_TSIF_INACTIVITY_TIMERS_CLK				106
116*4882a593Smuzhiyun #define GCC_TSIF_REF_CLK					107
117*4882a593Smuzhiyun #define GCC_UFS_AHB_CLK						108
118*4882a593Smuzhiyun #define GCC_UFS_AXI_CLK						109
119*4882a593Smuzhiyun #define GCC_UFS_ICE_CORE_CLK					110
120*4882a593Smuzhiyun #define GCC_UFS_PHY_AUX_CLK					111
121*4882a593Smuzhiyun #define GCC_UFS_RX_SYMBOL_0_CLK					112
122*4882a593Smuzhiyun #define GCC_UFS_RX_SYMBOL_1_CLK					113
123*4882a593Smuzhiyun #define GCC_UFS_TX_SYMBOL_0_CLK					114
124*4882a593Smuzhiyun #define GCC_UFS_UNIPRO_CORE_CLK					115
125*4882a593Smuzhiyun #define GCC_USB30_MASTER_CLK					116
126*4882a593Smuzhiyun #define GCC_USB30_MOCK_UTMI_CLK					117
127*4882a593Smuzhiyun #define GCC_USB30_SLEEP_CLK					118
128*4882a593Smuzhiyun #define GCC_USB3_PHY_AUX_CLK					119
129*4882a593Smuzhiyun #define GCC_USB3_PHY_PIPE_CLK					120
130*4882a593Smuzhiyun #define GCC_USB_PHY_CFG_AHB2PHY_CLK				121
131*4882a593Smuzhiyun #define GP1_CLK_SRC						122
132*4882a593Smuzhiyun #define GP2_CLK_SRC						123
133*4882a593Smuzhiyun #define GP3_CLK_SRC						124
134*4882a593Smuzhiyun #define GPLL0							125
135*4882a593Smuzhiyun #define GPLL0_OUT_EVEN						126
136*4882a593Smuzhiyun #define GPLL0_OUT_MAIN						127
137*4882a593Smuzhiyun #define GPLL0_OUT_ODD						128
138*4882a593Smuzhiyun #define GPLL0_OUT_TEST						129
139*4882a593Smuzhiyun #define GPLL1							130
140*4882a593Smuzhiyun #define GPLL1_OUT_EVEN						131
141*4882a593Smuzhiyun #define GPLL1_OUT_MAIN						132
142*4882a593Smuzhiyun #define GPLL1_OUT_ODD						133
143*4882a593Smuzhiyun #define GPLL1_OUT_TEST						134
144*4882a593Smuzhiyun #define GPLL2							135
145*4882a593Smuzhiyun #define GPLL2_OUT_EVEN						136
146*4882a593Smuzhiyun #define GPLL2_OUT_MAIN						137
147*4882a593Smuzhiyun #define GPLL2_OUT_ODD						138
148*4882a593Smuzhiyun #define GPLL2_OUT_TEST						139
149*4882a593Smuzhiyun #define GPLL3							140
150*4882a593Smuzhiyun #define GPLL3_OUT_EVEN						141
151*4882a593Smuzhiyun #define GPLL3_OUT_MAIN						142
152*4882a593Smuzhiyun #define GPLL3_OUT_ODD						143
153*4882a593Smuzhiyun #define GPLL3_OUT_TEST						144
154*4882a593Smuzhiyun #define GPLL4							145
155*4882a593Smuzhiyun #define GPLL4_OUT_EVEN						146
156*4882a593Smuzhiyun #define GPLL4_OUT_MAIN						147
157*4882a593Smuzhiyun #define GPLL4_OUT_ODD						148
158*4882a593Smuzhiyun #define GPLL4_OUT_TEST						149
159*4882a593Smuzhiyun #define GPLL6							150
160*4882a593Smuzhiyun #define GPLL6_OUT_EVEN						151
161*4882a593Smuzhiyun #define GPLL6_OUT_MAIN						152
162*4882a593Smuzhiyun #define GPLL6_OUT_ODD						153
163*4882a593Smuzhiyun #define GPLL6_OUT_TEST						154
164*4882a593Smuzhiyun #define HMSS_AHB_CLK_SRC					155
165*4882a593Smuzhiyun #define HMSS_RBCPR_CLK_SRC					156
166*4882a593Smuzhiyun #define PCIE_AUX_CLK_SRC					157
167*4882a593Smuzhiyun #define PDM2_CLK_SRC						158
168*4882a593Smuzhiyun #define SDCC2_APPS_CLK_SRC					159
169*4882a593Smuzhiyun #define SDCC4_APPS_CLK_SRC					160
170*4882a593Smuzhiyun #define TSIF_REF_CLK_SRC					161
171*4882a593Smuzhiyun #define UFS_AXI_CLK_SRC						162
172*4882a593Smuzhiyun #define USB30_MASTER_CLK_SRC					163
173*4882a593Smuzhiyun #define USB30_MOCK_UTMI_CLK_SRC					164
174*4882a593Smuzhiyun #define USB3_PHY_AUX_CLK_SRC					165
175*4882a593Smuzhiyun #define GCC_USB3_CLKREF_CLK					166
176*4882a593Smuzhiyun #define GCC_HDMI_CLKREF_CLK					167
177*4882a593Smuzhiyun #define GCC_UFS_CLKREF_CLK					168
178*4882a593Smuzhiyun #define GCC_PCIE_CLKREF_CLK					169
179*4882a593Smuzhiyun #define GCC_RX1_USB2_CLKREF_CLK					170
180*4882a593Smuzhiyun #define GCC_MSS_CFG_AHB_CLK					171
181*4882a593Smuzhiyun #define GCC_BOOT_ROM_AHB_CLK					172
182*4882a593Smuzhiyun #define GCC_MSS_GPLL0_DIV_CLK_SRC				173
183*4882a593Smuzhiyun #define GCC_MSS_SNOC_AXI_CLK					174
184*4882a593Smuzhiyun #define GCC_MSS_MNOC_BIMC_AXI_CLK				175
185*4882a593Smuzhiyun #define GCC_BIMC_GFX_CLK					176
186*4882a593Smuzhiyun #define UFS_UNIPRO_CORE_CLK_SRC					177
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun #define PCIE_0_GDSC						0
189*4882a593Smuzhiyun #define UFS_GDSC						1
190*4882a593Smuzhiyun #define USB_30_GDSC						2
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_BCR					0
193*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_BCR					1
194*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_BCR					2
195*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_BCR					3
196*4882a593Smuzhiyun #define GCC_BLSP1_QUP5_BCR					4
197*4882a593Smuzhiyun #define GCC_BLSP1_QUP6_BCR					5
198*4882a593Smuzhiyun #define GCC_BLSP2_QUP1_BCR					6
199*4882a593Smuzhiyun #define GCC_BLSP2_QUP2_BCR					7
200*4882a593Smuzhiyun #define GCC_BLSP2_QUP3_BCR					8
201*4882a593Smuzhiyun #define GCC_BLSP2_QUP4_BCR					9
202*4882a593Smuzhiyun #define GCC_BLSP2_QUP5_BCR					10
203*4882a593Smuzhiyun #define GCC_BLSP2_QUP6_BCR					11
204*4882a593Smuzhiyun #define GCC_PCIE_0_BCR						12
205*4882a593Smuzhiyun #define GCC_PDM_BCR						13
206*4882a593Smuzhiyun #define GCC_SDCC2_BCR						14
207*4882a593Smuzhiyun #define GCC_SDCC4_BCR						15
208*4882a593Smuzhiyun #define GCC_TSIF_BCR						16
209*4882a593Smuzhiyun #define GCC_UFS_BCR						17
210*4882a593Smuzhiyun #define GCC_USB_30_BCR						18
211*4882a593Smuzhiyun #define GCC_SYSTEM_NOC_BCR					19
212*4882a593Smuzhiyun #define GCC_CONFIG_NOC_BCR					20
213*4882a593Smuzhiyun #define GCC_AHB2PHY_EAST_BCR					21
214*4882a593Smuzhiyun #define GCC_IMEM_BCR						22
215*4882a593Smuzhiyun #define GCC_PIMEM_BCR						23
216*4882a593Smuzhiyun #define GCC_MMSS_BCR						24
217*4882a593Smuzhiyun #define GCC_QDSS_BCR						25
218*4882a593Smuzhiyun #define GCC_WCSS_BCR						26
219*4882a593Smuzhiyun #define GCC_BLSP1_BCR						27
220*4882a593Smuzhiyun #define GCC_BLSP1_UART1_BCR					28
221*4882a593Smuzhiyun #define GCC_BLSP1_UART2_BCR					29
222*4882a593Smuzhiyun #define GCC_BLSP1_UART3_BCR					30
223*4882a593Smuzhiyun #define GCC_CM_PHY_REFGEN1_BCR					31
224*4882a593Smuzhiyun #define GCC_CM_PHY_REFGEN2_BCR					32
225*4882a593Smuzhiyun #define GCC_BLSP2_BCR						33
226*4882a593Smuzhiyun #define GCC_BLSP2_UART1_BCR					34
227*4882a593Smuzhiyun #define GCC_BLSP2_UART2_BCR					35
228*4882a593Smuzhiyun #define GCC_BLSP2_UART3_BCR					36
229*4882a593Smuzhiyun #define GCC_SRAM_SENSOR_BCR					37
230*4882a593Smuzhiyun #define GCC_PRNG_BCR						38
231*4882a593Smuzhiyun #define GCC_TSIF_0_RESET					39
232*4882a593Smuzhiyun #define GCC_TSIF_1_RESET					40
233*4882a593Smuzhiyun #define GCC_TCSR_BCR						41
234*4882a593Smuzhiyun #define GCC_BOOT_ROM_BCR					42
235*4882a593Smuzhiyun #define GCC_MSG_RAM_BCR						43
236*4882a593Smuzhiyun #define GCC_TLMM_BCR						44
237*4882a593Smuzhiyun #define GCC_MPM_BCR						45
238*4882a593Smuzhiyun #define GCC_SEC_CTRL_BCR					46
239*4882a593Smuzhiyun #define GCC_SPMI_BCR						47
240*4882a593Smuzhiyun #define GCC_SPDM_BCR						48
241*4882a593Smuzhiyun #define GCC_CE1_BCR						49
242*4882a593Smuzhiyun #define GCC_BIMC_BCR						50
243*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT0_BCR				51
244*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT1_BCR				52
245*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT3_BCR				53
246*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR				54
247*4882a593Smuzhiyun #define GCC_PNOC_BUS_TIMEOUT0_BCR				55
248*4882a593Smuzhiyun #define GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR			56
249*4882a593Smuzhiyun #define GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR			57
250*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT0_BCR				58
251*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT1_BCR				59
252*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT2_BCR				60
253*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT3_BCR				61
254*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT4_BCR				62
255*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT5_BCR				63
256*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT6_BCR				64
257*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT7_BCR				65
258*4882a593Smuzhiyun #define GCC_APB2JTAG_BCR					66
259*4882a593Smuzhiyun #define GCC_RBCPR_CX_BCR					67
260*4882a593Smuzhiyun #define GCC_RBCPR_MX_BCR					68
261*4882a593Smuzhiyun #define GCC_USB3_PHY_BCR					69
262*4882a593Smuzhiyun #define GCC_USB3PHY_PHY_BCR					70
263*4882a593Smuzhiyun #define GCC_USB3_DP_PHY_BCR					71
264*4882a593Smuzhiyun #define GCC_SSC_BCR						72
265*4882a593Smuzhiyun #define GCC_SSC_RESET						73
266*4882a593Smuzhiyun #define GCC_USB_PHY_CFG_AHB2PHY_BCR				74
267*4882a593Smuzhiyun #define GCC_PCIE_0_LINK_DOWN_BCR				75
268*4882a593Smuzhiyun #define GCC_PCIE_0_PHY_BCR					76
269*4882a593Smuzhiyun #define GCC_PCIE_0_NOCSR_COM_PHY_BCR				77
270*4882a593Smuzhiyun #define GCC_PCIE_PHY_BCR					78
271*4882a593Smuzhiyun #define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR				79
272*4882a593Smuzhiyun #define GCC_PCIE_PHY_CFG_AHB_BCR				80
273*4882a593Smuzhiyun #define GCC_PCIE_PHY_COM_BCR					81
274*4882a593Smuzhiyun #define GCC_GPU_BCR						82
275*4882a593Smuzhiyun #define GCC_SPSS_BCR						83
276*4882a593Smuzhiyun #define GCC_OBT_ODT_BCR						84
277*4882a593Smuzhiyun #define GCC_VS_BCR						85
278*4882a593Smuzhiyun #define GCC_MSS_VS_RESET					86
279*4882a593Smuzhiyun #define GCC_GPU_VS_RESET					87
280*4882a593Smuzhiyun #define GCC_APC0_VS_RESET					88
281*4882a593Smuzhiyun #define GCC_APC1_VS_RESET					89
282*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT8_BCR				90
283*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT9_BCR				91
284*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT10_BCR				92
285*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT11_BCR				93
286*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT12_BCR				94
287*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT13_BCR				95
288*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT14_BCR				96
289*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR				97
290*4882a593Smuzhiyun #define GCC_AGGRE1_NOC_BCR					98
291*4882a593Smuzhiyun #define GCC_AGGRE2_NOC_BCR					99
292*4882a593Smuzhiyun #define GCC_DCC_BCR						100
293*4882a593Smuzhiyun #define GCC_QREFS_VBG_CAL_BCR					101
294*4882a593Smuzhiyun #define GCC_IPA_BCR						102
295*4882a593Smuzhiyun #define GCC_GLM_BCR						103
296*4882a593Smuzhiyun #define GCC_SKL_BCR						104
297*4882a593Smuzhiyun #define GCC_MSMPU_BCR						105
298*4882a593Smuzhiyun #define GCC_QUSB2PHY_PRIM_BCR					106
299*4882a593Smuzhiyun #define GCC_QUSB2PHY_SEC_BCR					107
300*4882a593Smuzhiyun #define GCC_MSS_RESTART						108
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun #endif
303