1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MSM_GCC_8996_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define GPLL0_EARLY 0 10*4882a593Smuzhiyun #define GPLL0 1 11*4882a593Smuzhiyun #define GPLL1_EARLY 2 12*4882a593Smuzhiyun #define GPLL1 3 13*4882a593Smuzhiyun #define GPLL2_EARLY 4 14*4882a593Smuzhiyun #define GPLL2 5 15*4882a593Smuzhiyun #define GPLL3_EARLY 6 16*4882a593Smuzhiyun #define GPLL3 7 17*4882a593Smuzhiyun #define GPLL4_EARLY 8 18*4882a593Smuzhiyun #define GPLL4 9 19*4882a593Smuzhiyun #define SYSTEM_NOC_CLK_SRC 10 20*4882a593Smuzhiyun #define CONFIG_NOC_CLK_SRC 11 21*4882a593Smuzhiyun #define PERIPH_NOC_CLK_SRC 12 22*4882a593Smuzhiyun #define MMSS_BIMC_GFX_CLK_SRC 13 23*4882a593Smuzhiyun #define USB30_MASTER_CLK_SRC 14 24*4882a593Smuzhiyun #define USB30_MOCK_UTMI_CLK_SRC 15 25*4882a593Smuzhiyun #define USB3_PHY_AUX_CLK_SRC 16 26*4882a593Smuzhiyun #define USB20_MASTER_CLK_SRC 17 27*4882a593Smuzhiyun #define USB20_MOCK_UTMI_CLK_SRC 18 28*4882a593Smuzhiyun #define SDCC1_APPS_CLK_SRC 19 29*4882a593Smuzhiyun #define SDCC1_ICE_CORE_CLK_SRC 20 30*4882a593Smuzhiyun #define SDCC2_APPS_CLK_SRC 21 31*4882a593Smuzhiyun #define SDCC3_APPS_CLK_SRC 22 32*4882a593Smuzhiyun #define SDCC4_APPS_CLK_SRC 23 33*4882a593Smuzhiyun #define BLSP1_QUP1_SPI_APPS_CLK_SRC 24 34*4882a593Smuzhiyun #define BLSP1_QUP1_I2C_APPS_CLK_SRC 25 35*4882a593Smuzhiyun #define BLSP1_UART1_APPS_CLK_SRC 26 36*4882a593Smuzhiyun #define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 37*4882a593Smuzhiyun #define BLSP1_QUP2_I2C_APPS_CLK_SRC 28 38*4882a593Smuzhiyun #define BLSP1_UART2_APPS_CLK_SRC 29 39*4882a593Smuzhiyun #define BLSP1_QUP3_SPI_APPS_CLK_SRC 30 40*4882a593Smuzhiyun #define BLSP1_QUP3_I2C_APPS_CLK_SRC 31 41*4882a593Smuzhiyun #define BLSP1_UART3_APPS_CLK_SRC 32 42*4882a593Smuzhiyun #define BLSP1_QUP4_SPI_APPS_CLK_SRC 33 43*4882a593Smuzhiyun #define BLSP1_QUP4_I2C_APPS_CLK_SRC 34 44*4882a593Smuzhiyun #define BLSP1_UART4_APPS_CLK_SRC 35 45*4882a593Smuzhiyun #define BLSP1_QUP5_SPI_APPS_CLK_SRC 36 46*4882a593Smuzhiyun #define BLSP1_QUP5_I2C_APPS_CLK_SRC 37 47*4882a593Smuzhiyun #define BLSP1_UART5_APPS_CLK_SRC 38 48*4882a593Smuzhiyun #define BLSP1_QUP6_SPI_APPS_CLK_SRC 39 49*4882a593Smuzhiyun #define BLSP1_QUP6_I2C_APPS_CLK_SRC 40 50*4882a593Smuzhiyun #define BLSP1_UART6_APPS_CLK_SRC 41 51*4882a593Smuzhiyun #define BLSP2_QUP1_SPI_APPS_CLK_SRC 42 52*4882a593Smuzhiyun #define BLSP2_QUP1_I2C_APPS_CLK_SRC 43 53*4882a593Smuzhiyun #define BLSP2_UART1_APPS_CLK_SRC 44 54*4882a593Smuzhiyun #define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 55*4882a593Smuzhiyun #define BLSP2_QUP2_I2C_APPS_CLK_SRC 46 56*4882a593Smuzhiyun #define BLSP2_UART2_APPS_CLK_SRC 47 57*4882a593Smuzhiyun #define BLSP2_QUP3_SPI_APPS_CLK_SRC 48 58*4882a593Smuzhiyun #define BLSP2_QUP3_I2C_APPS_CLK_SRC 49 59*4882a593Smuzhiyun #define BLSP2_UART3_APPS_CLK_SRC 50 60*4882a593Smuzhiyun #define BLSP2_QUP4_SPI_APPS_CLK_SRC 51 61*4882a593Smuzhiyun #define BLSP2_QUP4_I2C_APPS_CLK_SRC 52 62*4882a593Smuzhiyun #define BLSP2_UART4_APPS_CLK_SRC 53 63*4882a593Smuzhiyun #define BLSP2_QUP5_SPI_APPS_CLK_SRC 54 64*4882a593Smuzhiyun #define BLSP2_QUP5_I2C_APPS_CLK_SRC 55 65*4882a593Smuzhiyun #define BLSP2_UART5_APPS_CLK_SRC 56 66*4882a593Smuzhiyun #define BLSP2_QUP6_SPI_APPS_CLK_SRC 57 67*4882a593Smuzhiyun #define BLSP2_QUP6_I2C_APPS_CLK_SRC 58 68*4882a593Smuzhiyun #define BLSP2_UART6_APPS_CLK_SRC 59 69*4882a593Smuzhiyun #define PDM2_CLK_SRC 60 70*4882a593Smuzhiyun #define TSIF_REF_CLK_SRC 61 71*4882a593Smuzhiyun #define CE1_CLK_SRC 62 72*4882a593Smuzhiyun #define GCC_SLEEP_CLK_SRC 63 73*4882a593Smuzhiyun #define BIMC_CLK_SRC 64 74*4882a593Smuzhiyun #define HMSS_AHB_CLK_SRC 65 75*4882a593Smuzhiyun #define BIMC_HMSS_AXI_CLK_SRC 66 76*4882a593Smuzhiyun #define HMSS_RBCPR_CLK_SRC 67 77*4882a593Smuzhiyun #define HMSS_GPLL0_CLK_SRC 68 78*4882a593Smuzhiyun #define GP1_CLK_SRC 69 79*4882a593Smuzhiyun #define GP2_CLK_SRC 70 80*4882a593Smuzhiyun #define GP3_CLK_SRC 71 81*4882a593Smuzhiyun #define PCIE_AUX_CLK_SRC 72 82*4882a593Smuzhiyun #define UFS_AXI_CLK_SRC 73 83*4882a593Smuzhiyun #define UFS_ICE_CORE_CLK_SRC 74 84*4882a593Smuzhiyun #define QSPI_SER_CLK_SRC 75 85*4882a593Smuzhiyun #define GCC_SYS_NOC_AXI_CLK 76 86*4882a593Smuzhiyun #define GCC_SYS_NOC_HMSS_AHB_CLK 77 87*4882a593Smuzhiyun #define GCC_SNOC_CNOC_AHB_CLK 78 88*4882a593Smuzhiyun #define GCC_SNOC_PNOC_AHB_CLK 79 89*4882a593Smuzhiyun #define GCC_SYS_NOC_AT_CLK 80 90*4882a593Smuzhiyun #define GCC_SYS_NOC_USB3_AXI_CLK 81 91*4882a593Smuzhiyun #define GCC_SYS_NOC_UFS_AXI_CLK 82 92*4882a593Smuzhiyun #define GCC_CFG_NOC_AHB_CLK 83 93*4882a593Smuzhiyun #define GCC_PERIPH_NOC_AHB_CLK 84 94*4882a593Smuzhiyun #define GCC_PERIPH_NOC_USB20_AHB_CLK 85 95*4882a593Smuzhiyun #define GCC_TIC_CLK 86 96*4882a593Smuzhiyun #define GCC_IMEM_AXI_CLK 87 97*4882a593Smuzhiyun #define GCC_MMSS_SYS_NOC_AXI_CLK 88 98*4882a593Smuzhiyun #define GCC_MMSS_NOC_CFG_AHB_CLK 89 99*4882a593Smuzhiyun #define GCC_MMSS_BIMC_GFX_CLK 90 100*4882a593Smuzhiyun #define GCC_USB30_MASTER_CLK 91 101*4882a593Smuzhiyun #define GCC_USB30_SLEEP_CLK 92 102*4882a593Smuzhiyun #define GCC_USB30_MOCK_UTMI_CLK 93 103*4882a593Smuzhiyun #define GCC_USB3_PHY_AUX_CLK 94 104*4882a593Smuzhiyun #define GCC_USB3_PHY_PIPE_CLK 95 105*4882a593Smuzhiyun #define GCC_USB20_MASTER_CLK 96 106*4882a593Smuzhiyun #define GCC_USB20_SLEEP_CLK 97 107*4882a593Smuzhiyun #define GCC_USB20_MOCK_UTMI_CLK 98 108*4882a593Smuzhiyun #define GCC_USB_PHY_CFG_AHB2PHY_CLK 99 109*4882a593Smuzhiyun #define GCC_SDCC1_APPS_CLK 100 110*4882a593Smuzhiyun #define GCC_SDCC1_AHB_CLK 101 111*4882a593Smuzhiyun #define GCC_SDCC1_ICE_CORE_CLK 102 112*4882a593Smuzhiyun #define GCC_SDCC2_APPS_CLK 103 113*4882a593Smuzhiyun #define GCC_SDCC2_AHB_CLK 104 114*4882a593Smuzhiyun #define GCC_SDCC3_APPS_CLK 105 115*4882a593Smuzhiyun #define GCC_SDCC3_AHB_CLK 106 116*4882a593Smuzhiyun #define GCC_SDCC4_APPS_CLK 107 117*4882a593Smuzhiyun #define GCC_SDCC4_AHB_CLK 108 118*4882a593Smuzhiyun #define GCC_BLSP1_AHB_CLK 109 119*4882a593Smuzhiyun #define GCC_BLSP1_SLEEP_CLK 110 120*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_SPI_APPS_CLK 111 121*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_I2C_APPS_CLK 112 122*4882a593Smuzhiyun #define GCC_BLSP1_UART1_APPS_CLK 113 123*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_SPI_APPS_CLK 114 124*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_I2C_APPS_CLK 115 125*4882a593Smuzhiyun #define GCC_BLSP1_UART2_APPS_CLK 116 126*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_SPI_APPS_CLK 117 127*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_I2C_APPS_CLK 118 128*4882a593Smuzhiyun #define GCC_BLSP1_UART3_APPS_CLK 119 129*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_SPI_APPS_CLK 120 130*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_I2C_APPS_CLK 121 131*4882a593Smuzhiyun #define GCC_BLSP1_UART4_APPS_CLK 122 132*4882a593Smuzhiyun #define GCC_BLSP1_QUP5_SPI_APPS_CLK 123 133*4882a593Smuzhiyun #define GCC_BLSP1_QUP5_I2C_APPS_CLK 124 134*4882a593Smuzhiyun #define GCC_BLSP1_UART5_APPS_CLK 125 135*4882a593Smuzhiyun #define GCC_BLSP1_QUP6_SPI_APPS_CLK 126 136*4882a593Smuzhiyun #define GCC_BLSP1_QUP6_I2C_APPS_CLK 127 137*4882a593Smuzhiyun #define GCC_BLSP1_UART6_APPS_CLK 128 138*4882a593Smuzhiyun #define GCC_BLSP2_AHB_CLK 129 139*4882a593Smuzhiyun #define GCC_BLSP2_SLEEP_CLK 130 140*4882a593Smuzhiyun #define GCC_BLSP2_QUP1_SPI_APPS_CLK 131 141*4882a593Smuzhiyun #define GCC_BLSP2_QUP1_I2C_APPS_CLK 132 142*4882a593Smuzhiyun #define GCC_BLSP2_UART1_APPS_CLK 133 143*4882a593Smuzhiyun #define GCC_BLSP2_QUP2_SPI_APPS_CLK 134 144*4882a593Smuzhiyun #define GCC_BLSP2_QUP2_I2C_APPS_CLK 135 145*4882a593Smuzhiyun #define GCC_BLSP2_UART2_APPS_CLK 136 146*4882a593Smuzhiyun #define GCC_BLSP2_QUP3_SPI_APPS_CLK 137 147*4882a593Smuzhiyun #define GCC_BLSP2_QUP3_I2C_APPS_CLK 138 148*4882a593Smuzhiyun #define GCC_BLSP2_UART3_APPS_CLK 139 149*4882a593Smuzhiyun #define GCC_BLSP2_QUP4_SPI_APPS_CLK 140 150*4882a593Smuzhiyun #define GCC_BLSP2_QUP4_I2C_APPS_CLK 141 151*4882a593Smuzhiyun #define GCC_BLSP2_UART4_APPS_CLK 142 152*4882a593Smuzhiyun #define GCC_BLSP2_QUP5_SPI_APPS_CLK 143 153*4882a593Smuzhiyun #define GCC_BLSP2_QUP5_I2C_APPS_CLK 144 154*4882a593Smuzhiyun #define GCC_BLSP2_UART5_APPS_CLK 145 155*4882a593Smuzhiyun #define GCC_BLSP2_QUP6_SPI_APPS_CLK 146 156*4882a593Smuzhiyun #define GCC_BLSP2_QUP6_I2C_APPS_CLK 147 157*4882a593Smuzhiyun #define GCC_BLSP2_UART6_APPS_CLK 148 158*4882a593Smuzhiyun #define GCC_PDM_AHB_CLK 149 159*4882a593Smuzhiyun #define GCC_PDM_XO4_CLK 150 160*4882a593Smuzhiyun #define GCC_PDM2_CLK 151 161*4882a593Smuzhiyun #define GCC_PRNG_AHB_CLK 152 162*4882a593Smuzhiyun #define GCC_TSIF_AHB_CLK 153 163*4882a593Smuzhiyun #define GCC_TSIF_REF_CLK 154 164*4882a593Smuzhiyun #define GCC_TSIF_INACTIVITY_TIMERS_CLK 155 165*4882a593Smuzhiyun #define GCC_TCSR_AHB_CLK 156 166*4882a593Smuzhiyun #define GCC_BOOT_ROM_AHB_CLK 157 167*4882a593Smuzhiyun #define GCC_MSG_RAM_AHB_CLK 158 168*4882a593Smuzhiyun #define GCC_TLMM_AHB_CLK 159 169*4882a593Smuzhiyun #define GCC_TLMM_CLK 160 170*4882a593Smuzhiyun #define GCC_MPM_AHB_CLK 161 171*4882a593Smuzhiyun #define GCC_SPMI_SER_CLK 162 172*4882a593Smuzhiyun #define GCC_SPMI_CNOC_AHB_CLK 163 173*4882a593Smuzhiyun #define GCC_CE1_CLK 164 174*4882a593Smuzhiyun #define GCC_CE1_AXI_CLK 165 175*4882a593Smuzhiyun #define GCC_CE1_AHB_CLK 166 176*4882a593Smuzhiyun #define GCC_BIMC_HMSS_AXI_CLK 167 177*4882a593Smuzhiyun #define GCC_BIMC_GFX_CLK 168 178*4882a593Smuzhiyun #define GCC_HMSS_AHB_CLK 169 179*4882a593Smuzhiyun #define GCC_HMSS_SLV_AXI_CLK 170 180*4882a593Smuzhiyun #define GCC_HMSS_MSTR_AXI_CLK 171 181*4882a593Smuzhiyun #define GCC_HMSS_RBCPR_CLK 172 182*4882a593Smuzhiyun #define GCC_GP1_CLK 173 183*4882a593Smuzhiyun #define GCC_GP2_CLK 174 184*4882a593Smuzhiyun #define GCC_GP3_CLK 175 185*4882a593Smuzhiyun #define GCC_PCIE_0_SLV_AXI_CLK 176 186*4882a593Smuzhiyun #define GCC_PCIE_0_MSTR_AXI_CLK 177 187*4882a593Smuzhiyun #define GCC_PCIE_0_CFG_AHB_CLK 178 188*4882a593Smuzhiyun #define GCC_PCIE_0_AUX_CLK 179 189*4882a593Smuzhiyun #define GCC_PCIE_0_PIPE_CLK 180 190*4882a593Smuzhiyun #define GCC_PCIE_1_SLV_AXI_CLK 181 191*4882a593Smuzhiyun #define GCC_PCIE_1_MSTR_AXI_CLK 182 192*4882a593Smuzhiyun #define GCC_PCIE_1_CFG_AHB_CLK 183 193*4882a593Smuzhiyun #define GCC_PCIE_1_AUX_CLK 184 194*4882a593Smuzhiyun #define GCC_PCIE_1_PIPE_CLK 185 195*4882a593Smuzhiyun #define GCC_PCIE_2_SLV_AXI_CLK 186 196*4882a593Smuzhiyun #define GCC_PCIE_2_MSTR_AXI_CLK 187 197*4882a593Smuzhiyun #define GCC_PCIE_2_CFG_AHB_CLK 188 198*4882a593Smuzhiyun #define GCC_PCIE_2_AUX_CLK 189 199*4882a593Smuzhiyun #define GCC_PCIE_2_PIPE_CLK 190 200*4882a593Smuzhiyun #define GCC_PCIE_PHY_CFG_AHB_CLK 191 201*4882a593Smuzhiyun #define GCC_PCIE_PHY_AUX_CLK 192 202*4882a593Smuzhiyun #define GCC_UFS_AXI_CLK 193 203*4882a593Smuzhiyun #define GCC_UFS_AHB_CLK 194 204*4882a593Smuzhiyun #define GCC_UFS_TX_CFG_CLK 195 205*4882a593Smuzhiyun #define GCC_UFS_RX_CFG_CLK 196 206*4882a593Smuzhiyun #define GCC_UFS_TX_SYMBOL_0_CLK 197 207*4882a593Smuzhiyun #define GCC_UFS_RX_SYMBOL_0_CLK 198 208*4882a593Smuzhiyun #define GCC_UFS_RX_SYMBOL_1_CLK 199 209*4882a593Smuzhiyun #define GCC_UFS_UNIPRO_CORE_CLK 200 210*4882a593Smuzhiyun #define GCC_UFS_ICE_CORE_CLK 201 211*4882a593Smuzhiyun #define GCC_UFS_SYS_CLK_CORE_CLK 202 212*4882a593Smuzhiyun #define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK 203 213*4882a593Smuzhiyun #define GCC_AGGRE0_SNOC_AXI_CLK 204 214*4882a593Smuzhiyun #define GCC_AGGRE0_CNOC_AHB_CLK 205 215*4882a593Smuzhiyun #define GCC_SMMU_AGGRE0_AXI_CLK 206 216*4882a593Smuzhiyun #define GCC_SMMU_AGGRE0_AHB_CLK 207 217*4882a593Smuzhiyun #define GCC_AGGRE1_PNOC_AHB_CLK 208 218*4882a593Smuzhiyun #define GCC_AGGRE2_UFS_AXI_CLK 209 219*4882a593Smuzhiyun #define GCC_AGGRE2_USB3_AXI_CLK 210 220*4882a593Smuzhiyun #define GCC_QSPI_AHB_CLK 211 221*4882a593Smuzhiyun #define GCC_QSPI_SER_CLK 212 222*4882a593Smuzhiyun #define GCC_USB3_CLKREF_CLK 213 223*4882a593Smuzhiyun #define GCC_HDMI_CLKREF_CLK 214 224*4882a593Smuzhiyun #define GCC_UFS_CLKREF_CLK 215 225*4882a593Smuzhiyun #define GCC_PCIE_CLKREF_CLK 216 226*4882a593Smuzhiyun #define GCC_RX2_USB2_CLKREF_CLK 217 227*4882a593Smuzhiyun #define GCC_RX1_USB2_CLKREF_CLK 218 228*4882a593Smuzhiyun #define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219 229*4882a593Smuzhiyun #define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220 230*4882a593Smuzhiyun #define GCC_EDP_CLKREF_CLK 221 231*4882a593Smuzhiyun #define GCC_MSS_CFG_AHB_CLK 222 232*4882a593Smuzhiyun #define GCC_MSS_Q6_BIMC_AXI_CLK 223 233*4882a593Smuzhiyun #define GCC_MSS_SNOC_AXI_CLK 224 234*4882a593Smuzhiyun #define GCC_MSS_MNOC_BIMC_AXI_CLK 225 235*4882a593Smuzhiyun #define GCC_DCC_AHB_CLK 226 236*4882a593Smuzhiyun #define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 227 237*4882a593Smuzhiyun #define GCC_MMSS_GPLL0_DIV_CLK 228 238*4882a593Smuzhiyun #define GCC_MSS_GPLL0_DIV_CLK 229 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun #define GCC_SYSTEM_NOC_BCR 0 241*4882a593Smuzhiyun #define GCC_CONFIG_NOC_BCR 1 242*4882a593Smuzhiyun #define GCC_PERIPH_NOC_BCR 2 243*4882a593Smuzhiyun #define GCC_IMEM_BCR 3 244*4882a593Smuzhiyun #define GCC_MMSS_BCR 4 245*4882a593Smuzhiyun #define GCC_PIMEM_BCR 5 246*4882a593Smuzhiyun #define GCC_QDSS_BCR 6 247*4882a593Smuzhiyun #define GCC_USB_30_BCR 7 248*4882a593Smuzhiyun #define GCC_USB_20_BCR 8 249*4882a593Smuzhiyun #define GCC_QUSB2PHY_PRIM_BCR 9 250*4882a593Smuzhiyun #define GCC_QUSB2PHY_SEC_BCR 10 251*4882a593Smuzhiyun #define GCC_USB_PHY_CFG_AHB2PHY_BCR 11 252*4882a593Smuzhiyun #define GCC_SDCC1_BCR 12 253*4882a593Smuzhiyun #define GCC_SDCC2_BCR 13 254*4882a593Smuzhiyun #define GCC_SDCC3_BCR 14 255*4882a593Smuzhiyun #define GCC_SDCC4_BCR 15 256*4882a593Smuzhiyun #define GCC_BLSP1_BCR 16 257*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_BCR 17 258*4882a593Smuzhiyun #define GCC_BLSP1_UART1_BCR 18 259*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_BCR 19 260*4882a593Smuzhiyun #define GCC_BLSP1_UART2_BCR 20 261*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_BCR 21 262*4882a593Smuzhiyun #define GCC_BLSP1_UART3_BCR 22 263*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_BCR 23 264*4882a593Smuzhiyun #define GCC_BLSP1_UART4_BCR 24 265*4882a593Smuzhiyun #define GCC_BLSP1_QUP5_BCR 25 266*4882a593Smuzhiyun #define GCC_BLSP1_UART5_BCR 26 267*4882a593Smuzhiyun #define GCC_BLSP1_QUP6_BCR 27 268*4882a593Smuzhiyun #define GCC_BLSP1_UART6_BCR 28 269*4882a593Smuzhiyun #define GCC_BLSP2_BCR 29 270*4882a593Smuzhiyun #define GCC_BLSP2_QUP1_BCR 30 271*4882a593Smuzhiyun #define GCC_BLSP2_UART1_BCR 31 272*4882a593Smuzhiyun #define GCC_BLSP2_QUP2_BCR 32 273*4882a593Smuzhiyun #define GCC_BLSP2_UART2_BCR 33 274*4882a593Smuzhiyun #define GCC_BLSP2_QUP3_BCR 34 275*4882a593Smuzhiyun #define GCC_BLSP2_UART3_BCR 35 276*4882a593Smuzhiyun #define GCC_BLSP2_QUP4_BCR 36 277*4882a593Smuzhiyun #define GCC_BLSP2_UART4_BCR 37 278*4882a593Smuzhiyun #define GCC_BLSP2_QUP5_BCR 38 279*4882a593Smuzhiyun #define GCC_BLSP2_UART5_BCR 39 280*4882a593Smuzhiyun #define GCC_BLSP2_QUP6_BCR 40 281*4882a593Smuzhiyun #define GCC_BLSP2_UART6_BCR 41 282*4882a593Smuzhiyun #define GCC_PDM_BCR 42 283*4882a593Smuzhiyun #define GCC_PRNG_BCR 43 284*4882a593Smuzhiyun #define GCC_TSIF_BCR 44 285*4882a593Smuzhiyun #define GCC_TCSR_BCR 45 286*4882a593Smuzhiyun #define GCC_BOOT_ROM_BCR 46 287*4882a593Smuzhiyun #define GCC_MSG_RAM_BCR 47 288*4882a593Smuzhiyun #define GCC_TLMM_BCR 48 289*4882a593Smuzhiyun #define GCC_MPM_BCR 49 290*4882a593Smuzhiyun #define GCC_SEC_CTRL_BCR 50 291*4882a593Smuzhiyun #define GCC_SPMI_BCR 51 292*4882a593Smuzhiyun #define GCC_SPDM_BCR 52 293*4882a593Smuzhiyun #define GCC_CE1_BCR 53 294*4882a593Smuzhiyun #define GCC_BIMC_BCR 54 295*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT0_BCR 55 296*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT2_BCR 56 297*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT1_BCR 57 298*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT3_BCR 58 299*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 59 300*4882a593Smuzhiyun #define GCC_PNOC_BUS_TIMEOUT0_BCR 60 301*4882a593Smuzhiyun #define GCC_PNOC_BUS_TIMEOUT1_BCR 61 302*4882a593Smuzhiyun #define GCC_PNOC_BUS_TIMEOUT2_BCR 62 303*4882a593Smuzhiyun #define GCC_PNOC_BUS_TIMEOUT3_BCR 63 304*4882a593Smuzhiyun #define GCC_PNOC_BUS_TIMEOUT4_BCR 64 305*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT0_BCR 65 306*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT1_BCR 66 307*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT2_BCR 67 308*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT3_BCR 68 309*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT4_BCR 69 310*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT5_BCR 70 311*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT6_BCR 71 312*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT7_BCR 72 313*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT8_BCR 73 314*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT9_BCR 74 315*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 75 316*4882a593Smuzhiyun #define GCC_APB2JTAG_BCR 76 317*4882a593Smuzhiyun #define GCC_RBCPR_CX_BCR 77 318*4882a593Smuzhiyun #define GCC_RBCPR_MX_BCR 78 319*4882a593Smuzhiyun #define GCC_PCIE_0_BCR 79 320*4882a593Smuzhiyun #define GCC_PCIE_0_PHY_BCR 80 321*4882a593Smuzhiyun #define GCC_PCIE_1_BCR 81 322*4882a593Smuzhiyun #define GCC_PCIE_1_PHY_BCR 82 323*4882a593Smuzhiyun #define GCC_PCIE_2_BCR 83 324*4882a593Smuzhiyun #define GCC_PCIE_2_PHY_BCR 84 325*4882a593Smuzhiyun #define GCC_PCIE_PHY_BCR 85 326*4882a593Smuzhiyun #define GCC_DCD_BCR 86 327*4882a593Smuzhiyun #define GCC_OBT_ODT_BCR 87 328*4882a593Smuzhiyun #define GCC_UFS_BCR 88 329*4882a593Smuzhiyun #define GCC_SSC_BCR 89 330*4882a593Smuzhiyun #define GCC_VS_BCR 90 331*4882a593Smuzhiyun #define GCC_AGGRE0_NOC_BCR 91 332*4882a593Smuzhiyun #define GCC_AGGRE1_NOC_BCR 92 333*4882a593Smuzhiyun #define GCC_AGGRE2_NOC_BCR 93 334*4882a593Smuzhiyun #define GCC_DCC_BCR 94 335*4882a593Smuzhiyun #define GCC_IPA_BCR 95 336*4882a593Smuzhiyun #define GCC_QSPI_BCR 96 337*4882a593Smuzhiyun #define GCC_SKL_BCR 97 338*4882a593Smuzhiyun #define GCC_MSMPU_BCR 98 339*4882a593Smuzhiyun #define GCC_MSS_Q6_BCR 99 340*4882a593Smuzhiyun #define GCC_QREFS_VBG_CAL_BCR 100 341*4882a593Smuzhiyun #define GCC_PCIE_PHY_COM_BCR 101 342*4882a593Smuzhiyun #define GCC_PCIE_PHY_COM_NOCSR_BCR 102 343*4882a593Smuzhiyun #define GCC_USB3_PHY_BCR 103 344*4882a593Smuzhiyun #define GCC_USB3PHY_PHY_BCR 104 345*4882a593Smuzhiyun #define GCC_MSS_RESTART 105 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun /* Indexes for GDSCs */ 349*4882a593Smuzhiyun #define AGGRE0_NOC_GDSC 0 350*4882a593Smuzhiyun #define HLOS1_VOTE_AGGRE0_NOC_GDSC 1 351*4882a593Smuzhiyun #define HLOS1_VOTE_LPASS_ADSP_GDSC 2 352*4882a593Smuzhiyun #define HLOS1_VOTE_LPASS_CORE_GDSC 3 353*4882a593Smuzhiyun #define USB30_GDSC 4 354*4882a593Smuzhiyun #define PCIE0_GDSC 5 355*4882a593Smuzhiyun #define PCIE1_GDSC 6 356*4882a593Smuzhiyun #define PCIE2_GDSC 7 357*4882a593Smuzhiyun #define UFS_GDSC 8 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun #endif 360