1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2016, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MSM_GCC_8994_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MSM_GCC_8994_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define GPLL0_EARLY 0 11*4882a593Smuzhiyun #define GPLL0 1 12*4882a593Smuzhiyun #define GPLL4_EARLY 2 13*4882a593Smuzhiyun #define GPLL4 3 14*4882a593Smuzhiyun #define UFS_AXI_CLK_SRC 4 15*4882a593Smuzhiyun #define USB30_MASTER_CLK_SRC 5 16*4882a593Smuzhiyun #define BLSP1_QUP1_I2C_APPS_CLK_SRC 6 17*4882a593Smuzhiyun #define BLSP1_QUP1_SPI_APPS_CLK_SRC 7 18*4882a593Smuzhiyun #define BLSP1_QUP2_I2C_APPS_CLK_SRC 8 19*4882a593Smuzhiyun #define BLSP1_QUP2_SPI_APPS_CLK_SRC 9 20*4882a593Smuzhiyun #define BLSP1_QUP3_I2C_APPS_CLK_SRC 10 21*4882a593Smuzhiyun #define BLSP1_QUP3_SPI_APPS_CLK_SRC 11 22*4882a593Smuzhiyun #define BLSP1_QUP4_I2C_APPS_CLK_SRC 12 23*4882a593Smuzhiyun #define BLSP1_QUP4_SPI_APPS_CLK_SRC 13 24*4882a593Smuzhiyun #define BLSP1_QUP5_I2C_APPS_CLK_SRC 14 25*4882a593Smuzhiyun #define BLSP1_QUP5_SPI_APPS_CLK_SRC 15 26*4882a593Smuzhiyun #define BLSP1_QUP6_I2C_APPS_CLK_SRC 16 27*4882a593Smuzhiyun #define BLSP1_QUP6_SPI_APPS_CLK_SRC 17 28*4882a593Smuzhiyun #define BLSP1_UART1_APPS_CLK_SRC 18 29*4882a593Smuzhiyun #define BLSP1_UART2_APPS_CLK_SRC 19 30*4882a593Smuzhiyun #define BLSP1_UART3_APPS_CLK_SRC 20 31*4882a593Smuzhiyun #define BLSP1_UART4_APPS_CLK_SRC 21 32*4882a593Smuzhiyun #define BLSP1_UART5_APPS_CLK_SRC 22 33*4882a593Smuzhiyun #define BLSP1_UART6_APPS_CLK_SRC 23 34*4882a593Smuzhiyun #define BLSP2_QUP1_I2C_APPS_CLK_SRC 24 35*4882a593Smuzhiyun #define BLSP2_QUP1_SPI_APPS_CLK_SRC 25 36*4882a593Smuzhiyun #define BLSP2_QUP2_I2C_APPS_CLK_SRC 26 37*4882a593Smuzhiyun #define BLSP2_QUP2_SPI_APPS_CLK_SRC 27 38*4882a593Smuzhiyun #define BLSP2_QUP3_I2C_APPS_CLK_SRC 28 39*4882a593Smuzhiyun #define BLSP2_QUP3_SPI_APPS_CLK_SRC 29 40*4882a593Smuzhiyun #define BLSP2_QUP4_I2C_APPS_CLK_SRC 30 41*4882a593Smuzhiyun #define BLSP2_QUP4_SPI_APPS_CLK_SRC 31 42*4882a593Smuzhiyun #define BLSP2_QUP5_I2C_APPS_CLK_SRC 32 43*4882a593Smuzhiyun #define BLSP2_QUP5_SPI_APPS_CLK_SRC 33 44*4882a593Smuzhiyun #define BLSP2_QUP6_I2C_APPS_CLK_SRC 34 45*4882a593Smuzhiyun #define BLSP2_QUP6_SPI_APPS_CLK_SRC 35 46*4882a593Smuzhiyun #define BLSP2_UART1_APPS_CLK_SRC 36 47*4882a593Smuzhiyun #define BLSP2_UART2_APPS_CLK_SRC 37 48*4882a593Smuzhiyun #define BLSP2_UART3_APPS_CLK_SRC 38 49*4882a593Smuzhiyun #define BLSP2_UART4_APPS_CLK_SRC 39 50*4882a593Smuzhiyun #define BLSP2_UART5_APPS_CLK_SRC 40 51*4882a593Smuzhiyun #define BLSP2_UART6_APPS_CLK_SRC 41 52*4882a593Smuzhiyun #define GP1_CLK_SRC 42 53*4882a593Smuzhiyun #define GP2_CLK_SRC 43 54*4882a593Smuzhiyun #define GP3_CLK_SRC 44 55*4882a593Smuzhiyun #define PCIE_0_AUX_CLK_SRC 45 56*4882a593Smuzhiyun #define PCIE_0_PIPE_CLK_SRC 46 57*4882a593Smuzhiyun #define PCIE_1_AUX_CLK_SRC 47 58*4882a593Smuzhiyun #define PCIE_1_PIPE_CLK_SRC 48 59*4882a593Smuzhiyun #define PDM2_CLK_SRC 49 60*4882a593Smuzhiyun #define SDCC1_APPS_CLK_SRC 50 61*4882a593Smuzhiyun #define SDCC2_APPS_CLK_SRC 51 62*4882a593Smuzhiyun #define SDCC3_APPS_CLK_SRC 52 63*4882a593Smuzhiyun #define SDCC4_APPS_CLK_SRC 53 64*4882a593Smuzhiyun #define TSIF_REF_CLK_SRC 54 65*4882a593Smuzhiyun #define USB30_MOCK_UTMI_CLK_SRC 55 66*4882a593Smuzhiyun #define USB3_PHY_AUX_CLK_SRC 56 67*4882a593Smuzhiyun #define USB_HS_SYSTEM_CLK_SRC 57 68*4882a593Smuzhiyun #define GCC_BLSP1_AHB_CLK 58 69*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_I2C_APPS_CLK 59 70*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_SPI_APPS_CLK 60 71*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_I2C_APPS_CLK 61 72*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_SPI_APPS_CLK 62 73*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_I2C_APPS_CLK 63 74*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_SPI_APPS_CLK 64 75*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_I2C_APPS_CLK 65 76*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_SPI_APPS_CLK 66 77*4882a593Smuzhiyun #define GCC_BLSP1_QUP5_I2C_APPS_CLK 67 78*4882a593Smuzhiyun #define GCC_BLSP1_QUP5_SPI_APPS_CLK 68 79*4882a593Smuzhiyun #define GCC_BLSP1_QUP6_I2C_APPS_CLK 69 80*4882a593Smuzhiyun #define GCC_BLSP1_QUP6_SPI_APPS_CLK 70 81*4882a593Smuzhiyun #define GCC_BLSP1_UART1_APPS_CLK 71 82*4882a593Smuzhiyun #define GCC_BLSP1_UART2_APPS_CLK 72 83*4882a593Smuzhiyun #define GCC_BLSP1_UART3_APPS_CLK 73 84*4882a593Smuzhiyun #define GCC_BLSP1_UART4_APPS_CLK 74 85*4882a593Smuzhiyun #define GCC_BLSP1_UART5_APPS_CLK 75 86*4882a593Smuzhiyun #define GCC_BLSP1_UART6_APPS_CLK 76 87*4882a593Smuzhiyun #define GCC_BLSP2_AHB_CLK 77 88*4882a593Smuzhiyun #define GCC_BLSP2_QUP1_I2C_APPS_CLK 78 89*4882a593Smuzhiyun #define GCC_BLSP2_QUP1_SPI_APPS_CLK 79 90*4882a593Smuzhiyun #define GCC_BLSP2_QUP2_I2C_APPS_CLK 80 91*4882a593Smuzhiyun #define GCC_BLSP2_QUP2_SPI_APPS_CLK 81 92*4882a593Smuzhiyun #define GCC_BLSP2_QUP3_I2C_APPS_CLK 82 93*4882a593Smuzhiyun #define GCC_BLSP2_QUP3_SPI_APPS_CLK 83 94*4882a593Smuzhiyun #define GCC_BLSP2_QUP4_I2C_APPS_CLK 84 95*4882a593Smuzhiyun #define GCC_BLSP2_QUP4_SPI_APPS_CLK 85 96*4882a593Smuzhiyun #define GCC_BLSP2_QUP5_I2C_APPS_CLK 86 97*4882a593Smuzhiyun #define GCC_BLSP2_QUP5_SPI_APPS_CLK 87 98*4882a593Smuzhiyun #define GCC_BLSP2_QUP6_I2C_APPS_CLK 88 99*4882a593Smuzhiyun #define GCC_BLSP2_QUP6_SPI_APPS_CLK 89 100*4882a593Smuzhiyun #define GCC_BLSP2_UART1_APPS_CLK 90 101*4882a593Smuzhiyun #define GCC_BLSP2_UART2_APPS_CLK 91 102*4882a593Smuzhiyun #define GCC_BLSP2_UART3_APPS_CLK 92 103*4882a593Smuzhiyun #define GCC_BLSP2_UART4_APPS_CLK 93 104*4882a593Smuzhiyun #define GCC_BLSP2_UART5_APPS_CLK 94 105*4882a593Smuzhiyun #define GCC_BLSP2_UART6_APPS_CLK 95 106*4882a593Smuzhiyun #define GCC_GP1_CLK 96 107*4882a593Smuzhiyun #define GCC_GP2_CLK 97 108*4882a593Smuzhiyun #define GCC_GP3_CLK 98 109*4882a593Smuzhiyun #define GCC_PCIE_0_AUX_CLK 99 110*4882a593Smuzhiyun #define GCC_PCIE_0_PIPE_CLK 100 111*4882a593Smuzhiyun #define GCC_PCIE_1_AUX_CLK 101 112*4882a593Smuzhiyun #define GCC_PCIE_1_PIPE_CLK 102 113*4882a593Smuzhiyun #define GCC_PDM2_CLK 103 114*4882a593Smuzhiyun #define GCC_SDCC1_APPS_CLK 104 115*4882a593Smuzhiyun #define GCC_SDCC2_APPS_CLK 105 116*4882a593Smuzhiyun #define GCC_SDCC3_APPS_CLK 106 117*4882a593Smuzhiyun #define GCC_SDCC4_APPS_CLK 107 118*4882a593Smuzhiyun #define GCC_SYS_NOC_UFS_AXI_CLK 108 119*4882a593Smuzhiyun #define GCC_SYS_NOC_USB3_AXI_CLK 109 120*4882a593Smuzhiyun #define GCC_TSIF_REF_CLK 110 121*4882a593Smuzhiyun #define GCC_UFS_AXI_CLK 111 122*4882a593Smuzhiyun #define GCC_UFS_RX_CFG_CLK 112 123*4882a593Smuzhiyun #define GCC_UFS_TX_CFG_CLK 113 124*4882a593Smuzhiyun #define GCC_USB30_MASTER_CLK 114 125*4882a593Smuzhiyun #define GCC_USB30_MOCK_UTMI_CLK 115 126*4882a593Smuzhiyun #define GCC_USB3_PHY_AUX_CLK 116 127*4882a593Smuzhiyun #define GCC_USB_HS_SYSTEM_CLK 117 128*4882a593Smuzhiyun #define GCC_SDCC1_AHB_CLK 118 129*4882a593Smuzhiyun #define GCC_LPASS_Q6_AXI_CLK 119 130*4882a593Smuzhiyun #define GCC_MSS_Q6_BIMC_AXI_CLK 120 131*4882a593Smuzhiyun #define GCC_PCIE_0_CFG_AHB_CLK 121 132*4882a593Smuzhiyun #define GCC_PCIE_0_MSTR_AXI_CLK 122 133*4882a593Smuzhiyun #define GCC_PCIE_0_SLV_AXI_CLK 123 134*4882a593Smuzhiyun #define GCC_PCIE_1_CFG_AHB_CLK 124 135*4882a593Smuzhiyun #define GCC_PCIE_1_MSTR_AXI_CLK 125 136*4882a593Smuzhiyun #define GCC_PCIE_1_SLV_AXI_CLK 126 137*4882a593Smuzhiyun #define GCC_PDM_AHB_CLK 127 138*4882a593Smuzhiyun #define GCC_SDCC2_AHB_CLK 128 139*4882a593Smuzhiyun #define GCC_SDCC3_AHB_CLK 129 140*4882a593Smuzhiyun #define GCC_SDCC4_AHB_CLK 130 141*4882a593Smuzhiyun #define GCC_TSIF_AHB_CLK 131 142*4882a593Smuzhiyun #define GCC_UFS_AHB_CLK 132 143*4882a593Smuzhiyun #define GCC_UFS_RX_SYMBOL_0_CLK 133 144*4882a593Smuzhiyun #define GCC_UFS_RX_SYMBOL_1_CLK 134 145*4882a593Smuzhiyun #define GCC_UFS_TX_SYMBOL_0_CLK 135 146*4882a593Smuzhiyun #define GCC_UFS_TX_SYMBOL_1_CLK 136 147*4882a593Smuzhiyun #define GCC_USB2_HS_PHY_SLEEP_CLK 137 148*4882a593Smuzhiyun #define GCC_USB30_SLEEP_CLK 138 149*4882a593Smuzhiyun #define GCC_USB_HS_AHB_CLK 139 150*4882a593Smuzhiyun #define GCC_USB_PHY_CFG_AHB2PHY_CLK 140 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun /* GDSCs */ 153*4882a593Smuzhiyun #define PCIE_GDSC 0 154*4882a593Smuzhiyun #define PCIE_0_GDSC 1 155*4882a593Smuzhiyun #define PCIE_1_GDSC 2 156*4882a593Smuzhiyun #define USB30_GDSC 3 157*4882a593Smuzhiyun #define UFS_GDSC 4 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun /* Resets */ 160*4882a593Smuzhiyun #define USB3_PHY_RESET 0 161*4882a593Smuzhiyun #define USB3PHY_PHY_RESET 1 162*4882a593Smuzhiyun #define PCIE_PHY_0_RESET 2 163*4882a593Smuzhiyun #define PCIE_PHY_1_RESET 3 164*4882a593Smuzhiyun #define QUSB2_PHY_RESET 4 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun #endif 167