1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2013, The Linux Foundation. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MSM_GCC_8974_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MSM_GCC_8974_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define GPLL0 0 10*4882a593Smuzhiyun #define GPLL0_VOTE 1 11*4882a593Smuzhiyun #define CONFIG_NOC_CLK_SRC 2 12*4882a593Smuzhiyun #define GPLL2 3 13*4882a593Smuzhiyun #define GPLL2_VOTE 4 14*4882a593Smuzhiyun #define GPLL3 5 15*4882a593Smuzhiyun #define GPLL3_VOTE 6 16*4882a593Smuzhiyun #define PERIPH_NOC_CLK_SRC 7 17*4882a593Smuzhiyun #define BLSP_UART_SIM_CLK_SRC 8 18*4882a593Smuzhiyun #define QDSS_TSCTR_CLK_SRC 9 19*4882a593Smuzhiyun #define BIMC_DDR_CLK_SRC 10 20*4882a593Smuzhiyun #define SYSTEM_NOC_CLK_SRC 11 21*4882a593Smuzhiyun #define GPLL1 12 22*4882a593Smuzhiyun #define GPLL1_VOTE 13 23*4882a593Smuzhiyun #define RPM_CLK_SRC 14 24*4882a593Smuzhiyun #define GCC_BIMC_CLK 15 25*4882a593Smuzhiyun #define BIMC_DDR_CPLL0_ROOT_CLK_SRC 16 26*4882a593Smuzhiyun #define KPSS_AHB_CLK_SRC 17 27*4882a593Smuzhiyun #define QDSS_AT_CLK_SRC 18 28*4882a593Smuzhiyun #define USB30_MASTER_CLK_SRC 19 29*4882a593Smuzhiyun #define BIMC_DDR_CPLL1_ROOT_CLK_SRC 20 30*4882a593Smuzhiyun #define QDSS_STM_CLK_SRC 21 31*4882a593Smuzhiyun #define ACC_CLK_SRC 22 32*4882a593Smuzhiyun #define SEC_CTRL_CLK_SRC 23 33*4882a593Smuzhiyun #define BLSP1_QUP1_I2C_APPS_CLK_SRC 24 34*4882a593Smuzhiyun #define BLSP1_QUP1_SPI_APPS_CLK_SRC 25 35*4882a593Smuzhiyun #define BLSP1_QUP2_I2C_APPS_CLK_SRC 26 36*4882a593Smuzhiyun #define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 37*4882a593Smuzhiyun #define BLSP1_QUP3_I2C_APPS_CLK_SRC 28 38*4882a593Smuzhiyun #define BLSP1_QUP3_SPI_APPS_CLK_SRC 29 39*4882a593Smuzhiyun #define BLSP1_QUP4_I2C_APPS_CLK_SRC 30 40*4882a593Smuzhiyun #define BLSP1_QUP4_SPI_APPS_CLK_SRC 31 41*4882a593Smuzhiyun #define BLSP1_QUP5_I2C_APPS_CLK_SRC 32 42*4882a593Smuzhiyun #define BLSP1_QUP5_SPI_APPS_CLK_SRC 33 43*4882a593Smuzhiyun #define BLSP1_QUP6_I2C_APPS_CLK_SRC 34 44*4882a593Smuzhiyun #define BLSP1_QUP6_SPI_APPS_CLK_SRC 35 45*4882a593Smuzhiyun #define BLSP1_UART1_APPS_CLK_SRC 36 46*4882a593Smuzhiyun #define BLSP1_UART2_APPS_CLK_SRC 37 47*4882a593Smuzhiyun #define BLSP1_UART3_APPS_CLK_SRC 38 48*4882a593Smuzhiyun #define BLSP1_UART4_APPS_CLK_SRC 39 49*4882a593Smuzhiyun #define BLSP1_UART5_APPS_CLK_SRC 40 50*4882a593Smuzhiyun #define BLSP1_UART6_APPS_CLK_SRC 41 51*4882a593Smuzhiyun #define BLSP2_QUP1_I2C_APPS_CLK_SRC 42 52*4882a593Smuzhiyun #define BLSP2_QUP1_SPI_APPS_CLK_SRC 43 53*4882a593Smuzhiyun #define BLSP2_QUP2_I2C_APPS_CLK_SRC 44 54*4882a593Smuzhiyun #define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 55*4882a593Smuzhiyun #define BLSP2_QUP3_I2C_APPS_CLK_SRC 46 56*4882a593Smuzhiyun #define BLSP2_QUP3_SPI_APPS_CLK_SRC 47 57*4882a593Smuzhiyun #define BLSP2_QUP4_I2C_APPS_CLK_SRC 48 58*4882a593Smuzhiyun #define BLSP2_QUP4_SPI_APPS_CLK_SRC 49 59*4882a593Smuzhiyun #define BLSP2_QUP5_I2C_APPS_CLK_SRC 50 60*4882a593Smuzhiyun #define BLSP2_QUP5_SPI_APPS_CLK_SRC 51 61*4882a593Smuzhiyun #define BLSP2_QUP6_I2C_APPS_CLK_SRC 52 62*4882a593Smuzhiyun #define BLSP2_QUP6_SPI_APPS_CLK_SRC 53 63*4882a593Smuzhiyun #define BLSP2_UART1_APPS_CLK_SRC 54 64*4882a593Smuzhiyun #define BLSP2_UART2_APPS_CLK_SRC 55 65*4882a593Smuzhiyun #define BLSP2_UART3_APPS_CLK_SRC 56 66*4882a593Smuzhiyun #define BLSP2_UART4_APPS_CLK_SRC 57 67*4882a593Smuzhiyun #define BLSP2_UART5_APPS_CLK_SRC 58 68*4882a593Smuzhiyun #define BLSP2_UART6_APPS_CLK_SRC 59 69*4882a593Smuzhiyun #define CE1_CLK_SRC 60 70*4882a593Smuzhiyun #define CE2_CLK_SRC 61 71*4882a593Smuzhiyun #define GP1_CLK_SRC 62 72*4882a593Smuzhiyun #define GP2_CLK_SRC 63 73*4882a593Smuzhiyun #define GP3_CLK_SRC 64 74*4882a593Smuzhiyun #define PDM2_CLK_SRC 65 75*4882a593Smuzhiyun #define QDSS_TRACECLKIN_CLK_SRC 66 76*4882a593Smuzhiyun #define RBCPR_CLK_SRC 67 77*4882a593Smuzhiyun #define SDCC1_APPS_CLK_SRC 68 78*4882a593Smuzhiyun #define SDCC2_APPS_CLK_SRC 69 79*4882a593Smuzhiyun #define SDCC3_APPS_CLK_SRC 70 80*4882a593Smuzhiyun #define SDCC4_APPS_CLK_SRC 71 81*4882a593Smuzhiyun #define SPMI_AHB_CLK_SRC 72 82*4882a593Smuzhiyun #define SPMI_SER_CLK_SRC 73 83*4882a593Smuzhiyun #define TSIF_REF_CLK_SRC 74 84*4882a593Smuzhiyun #define USB30_MOCK_UTMI_CLK_SRC 75 85*4882a593Smuzhiyun #define USB_HS_SYSTEM_CLK_SRC 76 86*4882a593Smuzhiyun #define USB_HSIC_CLK_SRC 77 87*4882a593Smuzhiyun #define USB_HSIC_IO_CAL_CLK_SRC 78 88*4882a593Smuzhiyun #define USB_HSIC_SYSTEM_CLK_SRC 79 89*4882a593Smuzhiyun #define GCC_BAM_DMA_AHB_CLK 80 90*4882a593Smuzhiyun #define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 81 91*4882a593Smuzhiyun #define GCC_BIMC_CFG_AHB_CLK 82 92*4882a593Smuzhiyun #define GCC_BIMC_KPSS_AXI_CLK 83 93*4882a593Smuzhiyun #define GCC_BIMC_SLEEP_CLK 84 94*4882a593Smuzhiyun #define GCC_BIMC_SYSNOC_AXI_CLK 85 95*4882a593Smuzhiyun #define GCC_BIMC_XO_CLK 86 96*4882a593Smuzhiyun #define GCC_BLSP1_AHB_CLK 87 97*4882a593Smuzhiyun #define GCC_BLSP1_SLEEP_CLK 88 98*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_I2C_APPS_CLK 89 99*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_SPI_APPS_CLK 90 100*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_I2C_APPS_CLK 91 101*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_SPI_APPS_CLK 92 102*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_I2C_APPS_CLK 93 103*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_SPI_APPS_CLK 94 104*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_I2C_APPS_CLK 95 105*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_SPI_APPS_CLK 96 106*4882a593Smuzhiyun #define GCC_BLSP1_QUP5_I2C_APPS_CLK 97 107*4882a593Smuzhiyun #define GCC_BLSP1_QUP5_SPI_APPS_CLK 98 108*4882a593Smuzhiyun #define GCC_BLSP1_QUP6_I2C_APPS_CLK 99 109*4882a593Smuzhiyun #define GCC_BLSP1_QUP6_SPI_APPS_CLK 100 110*4882a593Smuzhiyun #define GCC_BLSP1_UART1_APPS_CLK 101 111*4882a593Smuzhiyun #define GCC_BLSP1_UART1_SIM_CLK 102 112*4882a593Smuzhiyun #define GCC_BLSP1_UART2_APPS_CLK 103 113*4882a593Smuzhiyun #define GCC_BLSP1_UART2_SIM_CLK 104 114*4882a593Smuzhiyun #define GCC_BLSP1_UART3_APPS_CLK 105 115*4882a593Smuzhiyun #define GCC_BLSP1_UART3_SIM_CLK 106 116*4882a593Smuzhiyun #define GCC_BLSP1_UART4_APPS_CLK 107 117*4882a593Smuzhiyun #define GCC_BLSP1_UART4_SIM_CLK 108 118*4882a593Smuzhiyun #define GCC_BLSP1_UART5_APPS_CLK 109 119*4882a593Smuzhiyun #define GCC_BLSP1_UART5_SIM_CLK 110 120*4882a593Smuzhiyun #define GCC_BLSP1_UART6_APPS_CLK 111 121*4882a593Smuzhiyun #define GCC_BLSP1_UART6_SIM_CLK 112 122*4882a593Smuzhiyun #define GCC_BLSP2_AHB_CLK 113 123*4882a593Smuzhiyun #define GCC_BLSP2_SLEEP_CLK 114 124*4882a593Smuzhiyun #define GCC_BLSP2_QUP1_I2C_APPS_CLK 115 125*4882a593Smuzhiyun #define GCC_BLSP2_QUP1_SPI_APPS_CLK 116 126*4882a593Smuzhiyun #define GCC_BLSP2_QUP2_I2C_APPS_CLK 117 127*4882a593Smuzhiyun #define GCC_BLSP2_QUP2_SPI_APPS_CLK 118 128*4882a593Smuzhiyun #define GCC_BLSP2_QUP3_I2C_APPS_CLK 119 129*4882a593Smuzhiyun #define GCC_BLSP2_QUP3_SPI_APPS_CLK 120 130*4882a593Smuzhiyun #define GCC_BLSP2_QUP4_I2C_APPS_CLK 121 131*4882a593Smuzhiyun #define GCC_BLSP2_QUP4_SPI_APPS_CLK 122 132*4882a593Smuzhiyun #define GCC_BLSP2_QUP5_I2C_APPS_CLK 123 133*4882a593Smuzhiyun #define GCC_BLSP2_QUP5_SPI_APPS_CLK 124 134*4882a593Smuzhiyun #define GCC_BLSP2_QUP6_I2C_APPS_CLK 125 135*4882a593Smuzhiyun #define GCC_BLSP2_QUP6_SPI_APPS_CLK 126 136*4882a593Smuzhiyun #define GCC_BLSP2_UART1_APPS_CLK 127 137*4882a593Smuzhiyun #define GCC_BLSP2_UART1_SIM_CLK 128 138*4882a593Smuzhiyun #define GCC_BLSP2_UART2_APPS_CLK 129 139*4882a593Smuzhiyun #define GCC_BLSP2_UART2_SIM_CLK 130 140*4882a593Smuzhiyun #define GCC_BLSP2_UART3_APPS_CLK 131 141*4882a593Smuzhiyun #define GCC_BLSP2_UART3_SIM_CLK 132 142*4882a593Smuzhiyun #define GCC_BLSP2_UART4_APPS_CLK 133 143*4882a593Smuzhiyun #define GCC_BLSP2_UART4_SIM_CLK 134 144*4882a593Smuzhiyun #define GCC_BLSP2_UART5_APPS_CLK 135 145*4882a593Smuzhiyun #define GCC_BLSP2_UART5_SIM_CLK 136 146*4882a593Smuzhiyun #define GCC_BLSP2_UART6_APPS_CLK 137 147*4882a593Smuzhiyun #define GCC_BLSP2_UART6_SIM_CLK 138 148*4882a593Smuzhiyun #define GCC_BOOT_ROM_AHB_CLK 139 149*4882a593Smuzhiyun #define GCC_CE1_AHB_CLK 140 150*4882a593Smuzhiyun #define GCC_CE1_AXI_CLK 141 151*4882a593Smuzhiyun #define GCC_CE1_CLK 142 152*4882a593Smuzhiyun #define GCC_CE2_AHB_CLK 143 153*4882a593Smuzhiyun #define GCC_CE2_AXI_CLK 144 154*4882a593Smuzhiyun #define GCC_CE2_CLK 145 155*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 146 156*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 147 157*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 148 158*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 149 159*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 150 160*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 151 161*4882a593Smuzhiyun #define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 152 162*4882a593Smuzhiyun #define GCC_CFG_NOC_AHB_CLK 153 163*4882a593Smuzhiyun #define GCC_CFG_NOC_DDR_CFG_CLK 154 164*4882a593Smuzhiyun #define GCC_CFG_NOC_RPM_AHB_CLK 155 165*4882a593Smuzhiyun #define GCC_BIMC_DDR_CPLL0_CLK 156 166*4882a593Smuzhiyun #define GCC_BIMC_DDR_CPLL1_CLK 157 167*4882a593Smuzhiyun #define GCC_DDR_DIM_CFG_CLK 158 168*4882a593Smuzhiyun #define GCC_DDR_DIM_SLEEP_CLK 159 169*4882a593Smuzhiyun #define GCC_DEHR_CLK 160 170*4882a593Smuzhiyun #define GCC_AHB_CLK 161 171*4882a593Smuzhiyun #define GCC_IM_SLEEP_CLK 162 172*4882a593Smuzhiyun #define GCC_XO_CLK 163 173*4882a593Smuzhiyun #define GCC_XO_DIV4_CLK 164 174*4882a593Smuzhiyun #define GCC_GP1_CLK 165 175*4882a593Smuzhiyun #define GCC_GP2_CLK 166 176*4882a593Smuzhiyun #define GCC_GP3_CLK 167 177*4882a593Smuzhiyun #define GCC_IMEM_AXI_CLK 168 178*4882a593Smuzhiyun #define GCC_IMEM_CFG_AHB_CLK 169 179*4882a593Smuzhiyun #define GCC_KPSS_AHB_CLK 170 180*4882a593Smuzhiyun #define GCC_KPSS_AXI_CLK 171 181*4882a593Smuzhiyun #define GCC_LPASS_Q6_AXI_CLK 172 182*4882a593Smuzhiyun #define GCC_MMSS_NOC_AT_CLK 173 183*4882a593Smuzhiyun #define GCC_MMSS_NOC_CFG_AHB_CLK 174 184*4882a593Smuzhiyun #define GCC_OCMEM_NOC_CFG_AHB_CLK 175 185*4882a593Smuzhiyun #define GCC_OCMEM_SYS_NOC_AXI_CLK 176 186*4882a593Smuzhiyun #define GCC_MPM_AHB_CLK 177 187*4882a593Smuzhiyun #define GCC_MSG_RAM_AHB_CLK 178 188*4882a593Smuzhiyun #define GCC_MSS_CFG_AHB_CLK 179 189*4882a593Smuzhiyun #define GCC_MSS_Q6_BIMC_AXI_CLK 180 190*4882a593Smuzhiyun #define GCC_NOC_CONF_XPU_AHB_CLK 181 191*4882a593Smuzhiyun #define GCC_PDM2_CLK 182 192*4882a593Smuzhiyun #define GCC_PDM_AHB_CLK 183 193*4882a593Smuzhiyun #define GCC_PDM_XO4_CLK 184 194*4882a593Smuzhiyun #define GCC_PERIPH_NOC_AHB_CLK 185 195*4882a593Smuzhiyun #define GCC_PERIPH_NOC_AT_CLK 186 196*4882a593Smuzhiyun #define GCC_PERIPH_NOC_CFG_AHB_CLK 187 197*4882a593Smuzhiyun #define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 188 198*4882a593Smuzhiyun #define GCC_PERIPH_XPU_AHB_CLK 189 199*4882a593Smuzhiyun #define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 190 200*4882a593Smuzhiyun #define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 191 201*4882a593Smuzhiyun #define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 192 202*4882a593Smuzhiyun #define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 193 203*4882a593Smuzhiyun #define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 194 204*4882a593Smuzhiyun #define GCC_PRNG_AHB_CLK 195 205*4882a593Smuzhiyun #define GCC_QDSS_AT_CLK 196 206*4882a593Smuzhiyun #define GCC_QDSS_CFG_AHB_CLK 197 207*4882a593Smuzhiyun #define GCC_QDSS_DAP_AHB_CLK 198 208*4882a593Smuzhiyun #define GCC_QDSS_DAP_CLK 199 209*4882a593Smuzhiyun #define GCC_QDSS_ETR_USB_CLK 200 210*4882a593Smuzhiyun #define GCC_QDSS_STM_CLK 201 211*4882a593Smuzhiyun #define GCC_QDSS_TRACECLKIN_CLK 202 212*4882a593Smuzhiyun #define GCC_QDSS_TSCTR_DIV16_CLK 203 213*4882a593Smuzhiyun #define GCC_QDSS_TSCTR_DIV2_CLK 204 214*4882a593Smuzhiyun #define GCC_QDSS_TSCTR_DIV3_CLK 205 215*4882a593Smuzhiyun #define GCC_QDSS_TSCTR_DIV4_CLK 206 216*4882a593Smuzhiyun #define GCC_QDSS_TSCTR_DIV8_CLK 207 217*4882a593Smuzhiyun #define GCC_QDSS_RBCPR_XPU_AHB_CLK 208 218*4882a593Smuzhiyun #define GCC_RBCPR_AHB_CLK 209 219*4882a593Smuzhiyun #define GCC_RBCPR_CLK 210 220*4882a593Smuzhiyun #define GCC_RPM_BUS_AHB_CLK 211 221*4882a593Smuzhiyun #define GCC_RPM_PROC_HCLK 212 222*4882a593Smuzhiyun #define GCC_RPM_SLEEP_CLK 213 223*4882a593Smuzhiyun #define GCC_RPM_TIMER_CLK 214 224*4882a593Smuzhiyun #define GCC_SDCC1_AHB_CLK 215 225*4882a593Smuzhiyun #define GCC_SDCC1_APPS_CLK 216 226*4882a593Smuzhiyun #define GCC_SDCC1_INACTIVITY_TIMERS_CLK 217 227*4882a593Smuzhiyun #define GCC_SDCC2_AHB_CLK 218 228*4882a593Smuzhiyun #define GCC_SDCC2_APPS_CLK 219 229*4882a593Smuzhiyun #define GCC_SDCC2_INACTIVITY_TIMERS_CLK 220 230*4882a593Smuzhiyun #define GCC_SDCC3_AHB_CLK 221 231*4882a593Smuzhiyun #define GCC_SDCC3_APPS_CLK 222 232*4882a593Smuzhiyun #define GCC_SDCC3_INACTIVITY_TIMERS_CLK 223 233*4882a593Smuzhiyun #define GCC_SDCC4_AHB_CLK 224 234*4882a593Smuzhiyun #define GCC_SDCC4_APPS_CLK 225 235*4882a593Smuzhiyun #define GCC_SDCC4_INACTIVITY_TIMERS_CLK 226 236*4882a593Smuzhiyun #define GCC_SEC_CTRL_ACC_CLK 227 237*4882a593Smuzhiyun #define GCC_SEC_CTRL_AHB_CLK 228 238*4882a593Smuzhiyun #define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 229 239*4882a593Smuzhiyun #define GCC_SEC_CTRL_CLK 230 240*4882a593Smuzhiyun #define GCC_SEC_CTRL_SENSE_CLK 231 241*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 232 242*4882a593Smuzhiyun #define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 233 243*4882a593Smuzhiyun #define GCC_SPDM_BIMC_CY_CLK 234 244*4882a593Smuzhiyun #define GCC_SPDM_CFG_AHB_CLK 235 245*4882a593Smuzhiyun #define GCC_SPDM_DEBUG_CY_CLK 236 246*4882a593Smuzhiyun #define GCC_SPDM_FF_CLK 237 247*4882a593Smuzhiyun #define GCC_SPDM_MSTR_AHB_CLK 238 248*4882a593Smuzhiyun #define GCC_SPDM_PNOC_CY_CLK 239 249*4882a593Smuzhiyun #define GCC_SPDM_RPM_CY_CLK 240 250*4882a593Smuzhiyun #define GCC_SPDM_SNOC_CY_CLK 241 251*4882a593Smuzhiyun #define GCC_SPMI_AHB_CLK 242 252*4882a593Smuzhiyun #define GCC_SPMI_CNOC_AHB_CLK 243 253*4882a593Smuzhiyun #define GCC_SPMI_SER_CLK 244 254*4882a593Smuzhiyun #define GCC_SNOC_CNOC_AHB_CLK 245 255*4882a593Smuzhiyun #define GCC_SNOC_PNOC_AHB_CLK 246 256*4882a593Smuzhiyun #define GCC_SYS_NOC_AT_CLK 247 257*4882a593Smuzhiyun #define GCC_SYS_NOC_AXI_CLK 248 258*4882a593Smuzhiyun #define GCC_SYS_NOC_KPSS_AHB_CLK 249 259*4882a593Smuzhiyun #define GCC_SYS_NOC_QDSS_STM_AXI_CLK 250 260*4882a593Smuzhiyun #define GCC_SYS_NOC_USB3_AXI_CLK 251 261*4882a593Smuzhiyun #define GCC_TCSR_AHB_CLK 252 262*4882a593Smuzhiyun #define GCC_TLMM_AHB_CLK 253 263*4882a593Smuzhiyun #define GCC_TLMM_CLK 254 264*4882a593Smuzhiyun #define GCC_TSIF_AHB_CLK 255 265*4882a593Smuzhiyun #define GCC_TSIF_INACTIVITY_TIMERS_CLK 256 266*4882a593Smuzhiyun #define GCC_TSIF_REF_CLK 257 267*4882a593Smuzhiyun #define GCC_USB2A_PHY_SLEEP_CLK 258 268*4882a593Smuzhiyun #define GCC_USB2B_PHY_SLEEP_CLK 259 269*4882a593Smuzhiyun #define GCC_USB30_MASTER_CLK 260 270*4882a593Smuzhiyun #define GCC_USB30_MOCK_UTMI_CLK 261 271*4882a593Smuzhiyun #define GCC_USB30_SLEEP_CLK 262 272*4882a593Smuzhiyun #define GCC_USB_HS_AHB_CLK 263 273*4882a593Smuzhiyun #define GCC_USB_HS_INACTIVITY_TIMERS_CLK 264 274*4882a593Smuzhiyun #define GCC_USB_HS_SYSTEM_CLK 265 275*4882a593Smuzhiyun #define GCC_USB_HSIC_AHB_CLK 266 276*4882a593Smuzhiyun #define GCC_USB_HSIC_CLK 267 277*4882a593Smuzhiyun #define GCC_USB_HSIC_IO_CAL_CLK 268 278*4882a593Smuzhiyun #define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 269 279*4882a593Smuzhiyun #define GCC_USB_HSIC_SYSTEM_CLK 270 280*4882a593Smuzhiyun #define GCC_WCSS_GPLL1_CLK_SRC 271 281*4882a593Smuzhiyun #define GCC_MMSS_GPLL0_CLK_SRC 272 282*4882a593Smuzhiyun #define GCC_LPASS_GPLL0_CLK_SRC 273 283*4882a593Smuzhiyun #define GCC_WCSS_GPLL1_CLK_SRC_SLEEP_ENA 274 284*4882a593Smuzhiyun #define GCC_MMSS_GPLL0_CLK_SRC_SLEEP_ENA 275 285*4882a593Smuzhiyun #define GCC_LPASS_GPLL0_CLK_SRC_SLEEP_ENA 276 286*4882a593Smuzhiyun #define GCC_IMEM_AXI_CLK_SLEEP_ENA 277 287*4882a593Smuzhiyun #define GCC_SYS_NOC_KPSS_AHB_CLK_SLEEP_ENA 278 288*4882a593Smuzhiyun #define GCC_BIMC_KPSS_AXI_CLK_SLEEP_ENA 279 289*4882a593Smuzhiyun #define GCC_KPSS_AHB_CLK_SLEEP_ENA 280 290*4882a593Smuzhiyun #define GCC_KPSS_AXI_CLK_SLEEP_ENA 281 291*4882a593Smuzhiyun #define GCC_MPM_AHB_CLK_SLEEP_ENA 282 292*4882a593Smuzhiyun #define GCC_OCMEM_SYS_NOC_AXI_CLK_SLEEP_ENA 283 293*4882a593Smuzhiyun #define GCC_BLSP1_AHB_CLK_SLEEP_ENA 284 294*4882a593Smuzhiyun #define GCC_BLSP1_SLEEP_CLK_SLEEP_ENA 285 295*4882a593Smuzhiyun #define GCC_BLSP2_AHB_CLK_SLEEP_ENA 286 296*4882a593Smuzhiyun #define GCC_BLSP2_SLEEP_CLK_SLEEP_ENA 287 297*4882a593Smuzhiyun #define GCC_PRNG_AHB_CLK_SLEEP_ENA 288 298*4882a593Smuzhiyun #define GCC_BAM_DMA_AHB_CLK_SLEEP_ENA 289 299*4882a593Smuzhiyun #define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK_SLEEP_ENA 290 300*4882a593Smuzhiyun #define GCC_BOOT_ROM_AHB_CLK_SLEEP_ENA 291 301*4882a593Smuzhiyun #define GCC_MSG_RAM_AHB_CLK_SLEEP_ENA 292 302*4882a593Smuzhiyun #define GCC_TLMM_AHB_CLK_SLEEP_ENA 293 303*4882a593Smuzhiyun #define GCC_TLMM_CLK_SLEEP_ENA 294 304*4882a593Smuzhiyun #define GCC_SPMI_CNOC_AHB_CLK_SLEEP_ENA 295 305*4882a593Smuzhiyun #define GCC_CE1_CLK_SLEEP_ENA 296 306*4882a593Smuzhiyun #define GCC_CE1_AXI_CLK_SLEEP_ENA 297 307*4882a593Smuzhiyun #define GCC_CE1_AHB_CLK_SLEEP_ENA 298 308*4882a593Smuzhiyun #define GCC_CE2_CLK_SLEEP_ENA 299 309*4882a593Smuzhiyun #define GCC_CE2_AXI_CLK_SLEEP_ENA 300 310*4882a593Smuzhiyun #define GCC_CE2_AHB_CLK_SLEEP_ENA 301 311*4882a593Smuzhiyun #define GPLL4 302 312*4882a593Smuzhiyun #define GPLL4_VOTE 303 313*4882a593Smuzhiyun #define GCC_SDCC1_CDCCAL_SLEEP_CLK 304 314*4882a593Smuzhiyun #define GCC_SDCC1_CDCCAL_FF_CLK 305 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun /* gdscs */ 317*4882a593Smuzhiyun #define USB_HS_HSIC_GDSC 0 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun #endif 320