1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2015 Linaro Limited 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MSM_GCC_8916_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MSM_GCC_8916_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define GPLL0 0 10*4882a593Smuzhiyun #define GPLL0_VOTE 1 11*4882a593Smuzhiyun #define BIMC_PLL 2 12*4882a593Smuzhiyun #define BIMC_PLL_VOTE 3 13*4882a593Smuzhiyun #define GPLL1 4 14*4882a593Smuzhiyun #define GPLL1_VOTE 5 15*4882a593Smuzhiyun #define GPLL2 6 16*4882a593Smuzhiyun #define GPLL2_VOTE 7 17*4882a593Smuzhiyun #define PCNOC_BFDCD_CLK_SRC 8 18*4882a593Smuzhiyun #define SYSTEM_NOC_BFDCD_CLK_SRC 9 19*4882a593Smuzhiyun #define CAMSS_AHB_CLK_SRC 10 20*4882a593Smuzhiyun #define APSS_AHB_CLK_SRC 11 21*4882a593Smuzhiyun #define CSI0_CLK_SRC 12 22*4882a593Smuzhiyun #define CSI1_CLK_SRC 13 23*4882a593Smuzhiyun #define GFX3D_CLK_SRC 14 24*4882a593Smuzhiyun #define VFE0_CLK_SRC 15 25*4882a593Smuzhiyun #define BLSP1_QUP1_I2C_APPS_CLK_SRC 16 26*4882a593Smuzhiyun #define BLSP1_QUP1_SPI_APPS_CLK_SRC 17 27*4882a593Smuzhiyun #define BLSP1_QUP2_I2C_APPS_CLK_SRC 18 28*4882a593Smuzhiyun #define BLSP1_QUP2_SPI_APPS_CLK_SRC 19 29*4882a593Smuzhiyun #define BLSP1_QUP3_I2C_APPS_CLK_SRC 20 30*4882a593Smuzhiyun #define BLSP1_QUP3_SPI_APPS_CLK_SRC 21 31*4882a593Smuzhiyun #define BLSP1_QUP4_I2C_APPS_CLK_SRC 22 32*4882a593Smuzhiyun #define BLSP1_QUP4_SPI_APPS_CLK_SRC 23 33*4882a593Smuzhiyun #define BLSP1_QUP5_I2C_APPS_CLK_SRC 24 34*4882a593Smuzhiyun #define BLSP1_QUP5_SPI_APPS_CLK_SRC 25 35*4882a593Smuzhiyun #define BLSP1_QUP6_I2C_APPS_CLK_SRC 26 36*4882a593Smuzhiyun #define BLSP1_QUP6_SPI_APPS_CLK_SRC 27 37*4882a593Smuzhiyun #define BLSP1_UART1_APPS_CLK_SRC 28 38*4882a593Smuzhiyun #define BLSP1_UART2_APPS_CLK_SRC 29 39*4882a593Smuzhiyun #define CCI_CLK_SRC 30 40*4882a593Smuzhiyun #define CAMSS_GP0_CLK_SRC 31 41*4882a593Smuzhiyun #define CAMSS_GP1_CLK_SRC 32 42*4882a593Smuzhiyun #define JPEG0_CLK_SRC 33 43*4882a593Smuzhiyun #define MCLK0_CLK_SRC 34 44*4882a593Smuzhiyun #define MCLK1_CLK_SRC 35 45*4882a593Smuzhiyun #define CSI0PHYTIMER_CLK_SRC 36 46*4882a593Smuzhiyun #define CSI1PHYTIMER_CLK_SRC 37 47*4882a593Smuzhiyun #define CPP_CLK_SRC 38 48*4882a593Smuzhiyun #define CRYPTO_CLK_SRC 39 49*4882a593Smuzhiyun #define GP1_CLK_SRC 40 50*4882a593Smuzhiyun #define GP2_CLK_SRC 41 51*4882a593Smuzhiyun #define GP3_CLK_SRC 42 52*4882a593Smuzhiyun #define BYTE0_CLK_SRC 43 53*4882a593Smuzhiyun #define ESC0_CLK_SRC 44 54*4882a593Smuzhiyun #define MDP_CLK_SRC 45 55*4882a593Smuzhiyun #define PCLK0_CLK_SRC 46 56*4882a593Smuzhiyun #define VSYNC_CLK_SRC 47 57*4882a593Smuzhiyun #define PDM2_CLK_SRC 48 58*4882a593Smuzhiyun #define SDCC1_APPS_CLK_SRC 49 59*4882a593Smuzhiyun #define SDCC2_APPS_CLK_SRC 50 60*4882a593Smuzhiyun #define APSS_TCU_CLK_SRC 51 61*4882a593Smuzhiyun #define USB_HS_SYSTEM_CLK_SRC 52 62*4882a593Smuzhiyun #define VCODEC0_CLK_SRC 53 63*4882a593Smuzhiyun #define GCC_BLSP1_AHB_CLK 54 64*4882a593Smuzhiyun #define GCC_BLSP1_SLEEP_CLK 55 65*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_I2C_APPS_CLK 56 66*4882a593Smuzhiyun #define GCC_BLSP1_QUP1_SPI_APPS_CLK 57 67*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_I2C_APPS_CLK 58 68*4882a593Smuzhiyun #define GCC_BLSP1_QUP2_SPI_APPS_CLK 59 69*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_I2C_APPS_CLK 60 70*4882a593Smuzhiyun #define GCC_BLSP1_QUP3_SPI_APPS_CLK 61 71*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_I2C_APPS_CLK 62 72*4882a593Smuzhiyun #define GCC_BLSP1_QUP4_SPI_APPS_CLK 63 73*4882a593Smuzhiyun #define GCC_BLSP1_QUP5_I2C_APPS_CLK 64 74*4882a593Smuzhiyun #define GCC_BLSP1_QUP5_SPI_APPS_CLK 65 75*4882a593Smuzhiyun #define GCC_BLSP1_QUP6_I2C_APPS_CLK 66 76*4882a593Smuzhiyun #define GCC_BLSP1_QUP6_SPI_APPS_CLK 67 77*4882a593Smuzhiyun #define GCC_BLSP1_UART1_APPS_CLK 68 78*4882a593Smuzhiyun #define GCC_BLSP1_UART2_APPS_CLK 69 79*4882a593Smuzhiyun #define GCC_BOOT_ROM_AHB_CLK 70 80*4882a593Smuzhiyun #define GCC_CAMSS_CCI_AHB_CLK 71 81*4882a593Smuzhiyun #define GCC_CAMSS_CCI_CLK 72 82*4882a593Smuzhiyun #define GCC_CAMSS_CSI0_AHB_CLK 73 83*4882a593Smuzhiyun #define GCC_CAMSS_CSI0_CLK 74 84*4882a593Smuzhiyun #define GCC_CAMSS_CSI0PHY_CLK 75 85*4882a593Smuzhiyun #define GCC_CAMSS_CSI0PIX_CLK 76 86*4882a593Smuzhiyun #define GCC_CAMSS_CSI0RDI_CLK 77 87*4882a593Smuzhiyun #define GCC_CAMSS_CSI1_AHB_CLK 78 88*4882a593Smuzhiyun #define GCC_CAMSS_CSI1_CLK 79 89*4882a593Smuzhiyun #define GCC_CAMSS_CSI1PHY_CLK 80 90*4882a593Smuzhiyun #define GCC_CAMSS_CSI1PIX_CLK 81 91*4882a593Smuzhiyun #define GCC_CAMSS_CSI1RDI_CLK 82 92*4882a593Smuzhiyun #define GCC_CAMSS_CSI_VFE0_CLK 83 93*4882a593Smuzhiyun #define GCC_CAMSS_GP0_CLK 84 94*4882a593Smuzhiyun #define GCC_CAMSS_GP1_CLK 85 95*4882a593Smuzhiyun #define GCC_CAMSS_ISPIF_AHB_CLK 86 96*4882a593Smuzhiyun #define GCC_CAMSS_JPEG0_CLK 87 97*4882a593Smuzhiyun #define GCC_CAMSS_JPEG_AHB_CLK 88 98*4882a593Smuzhiyun #define GCC_CAMSS_JPEG_AXI_CLK 89 99*4882a593Smuzhiyun #define GCC_CAMSS_MCLK0_CLK 90 100*4882a593Smuzhiyun #define GCC_CAMSS_MCLK1_CLK 91 101*4882a593Smuzhiyun #define GCC_CAMSS_MICRO_AHB_CLK 92 102*4882a593Smuzhiyun #define GCC_CAMSS_CSI0PHYTIMER_CLK 93 103*4882a593Smuzhiyun #define GCC_CAMSS_CSI1PHYTIMER_CLK 94 104*4882a593Smuzhiyun #define GCC_CAMSS_AHB_CLK 95 105*4882a593Smuzhiyun #define GCC_CAMSS_TOP_AHB_CLK 96 106*4882a593Smuzhiyun #define GCC_CAMSS_CPP_AHB_CLK 97 107*4882a593Smuzhiyun #define GCC_CAMSS_CPP_CLK 98 108*4882a593Smuzhiyun #define GCC_CAMSS_VFE0_CLK 99 109*4882a593Smuzhiyun #define GCC_CAMSS_VFE_AHB_CLK 100 110*4882a593Smuzhiyun #define GCC_CAMSS_VFE_AXI_CLK 101 111*4882a593Smuzhiyun #define GCC_CRYPTO_AHB_CLK 102 112*4882a593Smuzhiyun #define GCC_CRYPTO_AXI_CLK 103 113*4882a593Smuzhiyun #define GCC_CRYPTO_CLK 104 114*4882a593Smuzhiyun #define GCC_OXILI_GMEM_CLK 105 115*4882a593Smuzhiyun #define GCC_GP1_CLK 106 116*4882a593Smuzhiyun #define GCC_GP2_CLK 107 117*4882a593Smuzhiyun #define GCC_GP3_CLK 108 118*4882a593Smuzhiyun #define GCC_MDSS_AHB_CLK 109 119*4882a593Smuzhiyun #define GCC_MDSS_AXI_CLK 110 120*4882a593Smuzhiyun #define GCC_MDSS_BYTE0_CLK 111 121*4882a593Smuzhiyun #define GCC_MDSS_ESC0_CLK 112 122*4882a593Smuzhiyun #define GCC_MDSS_MDP_CLK 113 123*4882a593Smuzhiyun #define GCC_MDSS_PCLK0_CLK 114 124*4882a593Smuzhiyun #define GCC_MDSS_VSYNC_CLK 115 125*4882a593Smuzhiyun #define GCC_MSS_CFG_AHB_CLK 116 126*4882a593Smuzhiyun #define GCC_OXILI_AHB_CLK 117 127*4882a593Smuzhiyun #define GCC_OXILI_GFX3D_CLK 118 128*4882a593Smuzhiyun #define GCC_PDM2_CLK 119 129*4882a593Smuzhiyun #define GCC_PDM_AHB_CLK 120 130*4882a593Smuzhiyun #define GCC_PRNG_AHB_CLK 121 131*4882a593Smuzhiyun #define GCC_SDCC1_AHB_CLK 122 132*4882a593Smuzhiyun #define GCC_SDCC1_APPS_CLK 123 133*4882a593Smuzhiyun #define GCC_SDCC2_AHB_CLK 124 134*4882a593Smuzhiyun #define GCC_SDCC2_APPS_CLK 125 135*4882a593Smuzhiyun #define GCC_GTCU_AHB_CLK 126 136*4882a593Smuzhiyun #define GCC_JPEG_TBU_CLK 127 137*4882a593Smuzhiyun #define GCC_MDP_TBU_CLK 128 138*4882a593Smuzhiyun #define GCC_SMMU_CFG_CLK 129 139*4882a593Smuzhiyun #define GCC_VENUS_TBU_CLK 130 140*4882a593Smuzhiyun #define GCC_VFE_TBU_CLK 131 141*4882a593Smuzhiyun #define GCC_USB2A_PHY_SLEEP_CLK 132 142*4882a593Smuzhiyun #define GCC_USB_HS_AHB_CLK 133 143*4882a593Smuzhiyun #define GCC_USB_HS_SYSTEM_CLK 134 144*4882a593Smuzhiyun #define GCC_VENUS0_AHB_CLK 135 145*4882a593Smuzhiyun #define GCC_VENUS0_AXI_CLK 136 146*4882a593Smuzhiyun #define GCC_VENUS0_VCODEC0_CLK 137 147*4882a593Smuzhiyun #define BIMC_DDR_CLK_SRC 138 148*4882a593Smuzhiyun #define GCC_APSS_TCU_CLK 139 149*4882a593Smuzhiyun #define GCC_GFX_TCU_CLK 140 150*4882a593Smuzhiyun #define BIMC_GPU_CLK_SRC 141 151*4882a593Smuzhiyun #define GCC_BIMC_GFX_CLK 142 152*4882a593Smuzhiyun #define GCC_BIMC_GPU_CLK 143 153*4882a593Smuzhiyun #define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 144 154*4882a593Smuzhiyun #define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 145 155*4882a593Smuzhiyun #define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 146 156*4882a593Smuzhiyun #define ULTAUDIO_XO_CLK_SRC 147 157*4882a593Smuzhiyun #define ULTAUDIO_AHBFABRIC_CLK_SRC 148 158*4882a593Smuzhiyun #define CODEC_DIGCODEC_CLK_SRC 149 159*4882a593Smuzhiyun #define GCC_ULTAUDIO_PCNOC_MPORT_CLK 150 160*4882a593Smuzhiyun #define GCC_ULTAUDIO_PCNOC_SWAY_CLK 151 161*4882a593Smuzhiyun #define GCC_ULTAUDIO_AVSYNC_XO_CLK 152 162*4882a593Smuzhiyun #define GCC_ULTAUDIO_STC_XO_CLK 153 163*4882a593Smuzhiyun #define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 154 164*4882a593Smuzhiyun #define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 155 165*4882a593Smuzhiyun #define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 156 166*4882a593Smuzhiyun #define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 157 167*4882a593Smuzhiyun #define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 158 168*4882a593Smuzhiyun #define GCC_CODEC_DIGCODEC_CLK 159 169*4882a593Smuzhiyun #define GCC_MSS_Q6_BIMC_AXI_CLK 160 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* Indexes for GDSCs */ 172*4882a593Smuzhiyun #define BIMC_GDSC 0 173*4882a593Smuzhiyun #define VENUS_GDSC 1 174*4882a593Smuzhiyun #define MDSS_GDSC 2 175*4882a593Smuzhiyun #define JPEG_GDSC 3 176*4882a593Smuzhiyun #define VFE_GDSC 4 177*4882a593Smuzhiyun #define OXILI_GDSC 5 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun #endif 180