1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Inspired by original work from pxa2xx-regs.h by Nicolas Pitre 4*4882a593Smuzhiyun * Copyright (C) 2014 Robert Jarzmik 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_PXA2XX_H__ 8*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_PXA2XX_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define CLK_NONE 0 11*4882a593Smuzhiyun #define CLK_1WIRE 1 12*4882a593Smuzhiyun #define CLK_AC97 2 13*4882a593Smuzhiyun #define CLK_AC97CONF 3 14*4882a593Smuzhiyun #define CLK_ASSP 4 15*4882a593Smuzhiyun #define CLK_BOOT 5 16*4882a593Smuzhiyun #define CLK_BTUART 6 17*4882a593Smuzhiyun #define CLK_CAMERA 7 18*4882a593Smuzhiyun #define CLK_CIR 8 19*4882a593Smuzhiyun #define CLK_CORE 9 20*4882a593Smuzhiyun #define CLK_DMC 10 21*4882a593Smuzhiyun #define CLK_FFUART 11 22*4882a593Smuzhiyun #define CLK_FICP 12 23*4882a593Smuzhiyun #define CLK_GPIO 13 24*4882a593Smuzhiyun #define CLK_HSIO2 14 25*4882a593Smuzhiyun #define CLK_HWUART 15 26*4882a593Smuzhiyun #define CLK_I2C 16 27*4882a593Smuzhiyun #define CLK_I2S 17 28*4882a593Smuzhiyun #define CLK_IM 18 29*4882a593Smuzhiyun #define CLK_INC 19 30*4882a593Smuzhiyun #define CLK_ISC 20 31*4882a593Smuzhiyun #define CLK_KEYPAD 21 32*4882a593Smuzhiyun #define CLK_LCD 22 33*4882a593Smuzhiyun #define CLK_MEMC 23 34*4882a593Smuzhiyun #define CLK_MEMSTK 24 35*4882a593Smuzhiyun #define CLK_MINI_IM 25 36*4882a593Smuzhiyun #define CLK_MINI_LCD 26 37*4882a593Smuzhiyun #define CLK_MMC 27 38*4882a593Smuzhiyun #define CLK_MMC1 28 39*4882a593Smuzhiyun #define CLK_MMC2 29 40*4882a593Smuzhiyun #define CLK_MMC3 30 41*4882a593Smuzhiyun #define CLK_MSL 31 42*4882a593Smuzhiyun #define CLK_MSL0 32 43*4882a593Smuzhiyun #define CLK_MVED 33 44*4882a593Smuzhiyun #define CLK_NAND 34 45*4882a593Smuzhiyun #define CLK_NSSP 35 46*4882a593Smuzhiyun #define CLK_OSTIMER 36 47*4882a593Smuzhiyun #define CLK_PWM0 37 48*4882a593Smuzhiyun #define CLK_PWM1 38 49*4882a593Smuzhiyun #define CLK_PWM2 39 50*4882a593Smuzhiyun #define CLK_PWM3 40 51*4882a593Smuzhiyun #define CLK_PWRI2C 41 52*4882a593Smuzhiyun #define CLK_PXA300_GCU 42 53*4882a593Smuzhiyun #define CLK_PXA320_GCU 43 54*4882a593Smuzhiyun #define CLK_SMC 44 55*4882a593Smuzhiyun #define CLK_SSP 45 56*4882a593Smuzhiyun #define CLK_SSP1 46 57*4882a593Smuzhiyun #define CLK_SSP2 47 58*4882a593Smuzhiyun #define CLK_SSP3 48 59*4882a593Smuzhiyun #define CLK_SSP4 49 60*4882a593Smuzhiyun #define CLK_STUART 50 61*4882a593Smuzhiyun #define CLK_TOUCH 51 62*4882a593Smuzhiyun #define CLK_TPM 52 63*4882a593Smuzhiyun #define CLK_UDC 53 64*4882a593Smuzhiyun #define CLK_USB 54 65*4882a593Smuzhiyun #define CLK_USB2 55 66*4882a593Smuzhiyun #define CLK_USBH 56 67*4882a593Smuzhiyun #define CLK_USBHOST 57 68*4882a593Smuzhiyun #define CLK_USIM 58 69*4882a593Smuzhiyun #define CLK_USIM1 59 70*4882a593Smuzhiyun #define CLK_USMI0 60 71*4882a593Smuzhiyun #define CLK_OSC32k768 61 72*4882a593Smuzhiyun #define CLK_MAX 62 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #endif 75