1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef DT_CLOCK_OXSEMI_OX820_H 7*4882a593Smuzhiyun #define DT_CLOCK_OXSEMI_OX820_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* PLLs */ 10*4882a593Smuzhiyun #define CLK_820_PLLA 0 11*4882a593Smuzhiyun #define CLK_820_PLLB 1 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Gate Clocks */ 14*4882a593Smuzhiyun #define CLK_820_LEON 2 15*4882a593Smuzhiyun #define CLK_820_DMA_SGDMA 3 16*4882a593Smuzhiyun #define CLK_820_CIPHER 4 17*4882a593Smuzhiyun #define CLK_820_SD 5 18*4882a593Smuzhiyun #define CLK_820_SATA 6 19*4882a593Smuzhiyun #define CLK_820_AUDIO 7 20*4882a593Smuzhiyun #define CLK_820_USBMPH 8 21*4882a593Smuzhiyun #define CLK_820_ETHA 9 22*4882a593Smuzhiyun #define CLK_820_PCIEA 10 23*4882a593Smuzhiyun #define CLK_820_NAND 11 24*4882a593Smuzhiyun #define CLK_820_PCIEB 12 25*4882a593Smuzhiyun #define CLK_820_ETHB 13 26*4882a593Smuzhiyun #define CLK_820_REF600 14 27*4882a593Smuzhiyun #define CLK_820_USBDEV 15 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #endif /* DT_CLOCK_OXSEMI_OX820_H */ 30