xref: /OK3568_Linux_fs/kernel/include/dt-bindings/clock/omap5.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright 2017 Texas Instruments, Inc.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLK_OMAP5_H
6*4882a593Smuzhiyun #define __DT_BINDINGS_CLK_OMAP5_H
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #define OMAP5_CLKCTRL_OFFSET	0x20
9*4882a593Smuzhiyun #define OMAP5_CLKCTRL_INDEX(offset)	((offset) - OMAP5_CLKCTRL_OFFSET)
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun /* mpu clocks */
12*4882a593Smuzhiyun #define OMAP5_MPU_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun /* dsp clocks */
15*4882a593Smuzhiyun #define OMAP5_MMU_DSP_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun /* abe clocks */
18*4882a593Smuzhiyun #define OMAP5_L4_ABE_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
19*4882a593Smuzhiyun #define OMAP5_AESS_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x28)
20*4882a593Smuzhiyun #define OMAP5_MCPDM_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x30)
21*4882a593Smuzhiyun #define OMAP5_DMIC_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x38)
22*4882a593Smuzhiyun #define OMAP5_MCBSP1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x48)
23*4882a593Smuzhiyun #define OMAP5_MCBSP2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x50)
24*4882a593Smuzhiyun #define OMAP5_MCBSP3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x58)
25*4882a593Smuzhiyun #define OMAP5_TIMER5_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x68)
26*4882a593Smuzhiyun #define OMAP5_TIMER6_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x70)
27*4882a593Smuzhiyun #define OMAP5_TIMER7_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x78)
28*4882a593Smuzhiyun #define OMAP5_TIMER8_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x80)
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun /* l3main1 clocks */
31*4882a593Smuzhiyun #define OMAP5_L3_MAIN_1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun /* l3main2 clocks */
34*4882a593Smuzhiyun #define OMAP5_L3_MAIN_2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun /* ipu clocks */
37*4882a593Smuzhiyun #define OMAP5_MMU_IPU_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun /* dma clocks */
40*4882a593Smuzhiyun #define OMAP5_DMA_SYSTEM_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun /* emif clocks */
43*4882a593Smuzhiyun #define OMAP5_DMM_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
44*4882a593Smuzhiyun #define OMAP5_EMIF1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x30)
45*4882a593Smuzhiyun #define OMAP5_EMIF2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x38)
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun /* l4cfg clocks */
48*4882a593Smuzhiyun #define OMAP5_L4_CFG_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
49*4882a593Smuzhiyun #define OMAP5_SPINLOCK_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x28)
50*4882a593Smuzhiyun #define OMAP5_MAILBOX_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x30)
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun /* l3instr clocks */
53*4882a593Smuzhiyun #define OMAP5_L3_MAIN_3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
54*4882a593Smuzhiyun #define OMAP5_L3_INSTR_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x28)
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun /* l4per clocks */
57*4882a593Smuzhiyun #define OMAP5_TIMER10_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x28)
58*4882a593Smuzhiyun #define OMAP5_TIMER11_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x30)
59*4882a593Smuzhiyun #define OMAP5_TIMER2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x38)
60*4882a593Smuzhiyun #define OMAP5_TIMER3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x40)
61*4882a593Smuzhiyun #define OMAP5_TIMER4_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x48)
62*4882a593Smuzhiyun #define OMAP5_TIMER9_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x50)
63*4882a593Smuzhiyun #define OMAP5_GPIO2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x60)
64*4882a593Smuzhiyun #define OMAP5_GPIO3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x68)
65*4882a593Smuzhiyun #define OMAP5_GPIO4_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x70)
66*4882a593Smuzhiyun #define OMAP5_GPIO5_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x78)
67*4882a593Smuzhiyun #define OMAP5_GPIO6_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x80)
68*4882a593Smuzhiyun #define OMAP5_I2C1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xa0)
69*4882a593Smuzhiyun #define OMAP5_I2C2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xa8)
70*4882a593Smuzhiyun #define OMAP5_I2C3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xb0)
71*4882a593Smuzhiyun #define OMAP5_I2C4_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xb8)
72*4882a593Smuzhiyun #define OMAP5_L4_PER_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xc0)
73*4882a593Smuzhiyun #define OMAP5_MCSPI1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xf0)
74*4882a593Smuzhiyun #define OMAP5_MCSPI2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xf8)
75*4882a593Smuzhiyun #define OMAP5_MCSPI3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x100)
76*4882a593Smuzhiyun #define OMAP5_MCSPI4_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x108)
77*4882a593Smuzhiyun #define OMAP5_GPIO7_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x110)
78*4882a593Smuzhiyun #define OMAP5_GPIO8_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x118)
79*4882a593Smuzhiyun #define OMAP5_MMC3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x120)
80*4882a593Smuzhiyun #define OMAP5_MMC4_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x128)
81*4882a593Smuzhiyun #define OMAP5_UART1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x140)
82*4882a593Smuzhiyun #define OMAP5_UART2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x148)
83*4882a593Smuzhiyun #define OMAP5_UART3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x150)
84*4882a593Smuzhiyun #define OMAP5_UART4_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x158)
85*4882a593Smuzhiyun #define OMAP5_MMC5_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x160)
86*4882a593Smuzhiyun #define OMAP5_I2C5_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x168)
87*4882a593Smuzhiyun #define OMAP5_UART5_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x170)
88*4882a593Smuzhiyun #define OMAP5_UART6_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x178)
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun /* l4_secure clocks */
91*4882a593Smuzhiyun #define OMAP5_L4_SECURE_CLKCTRL_OFFSET	0x1a0
92*4882a593Smuzhiyun #define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset)	((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET)
93*4882a593Smuzhiyun #define OMAP5_AES1_CLKCTRL	OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0)
94*4882a593Smuzhiyun #define OMAP5_AES2_CLKCTRL	OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8)
95*4882a593Smuzhiyun #define OMAP5_DES3DES_CLKCTRL	OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0)
96*4882a593Smuzhiyun #define OMAP5_FPKA_CLKCTRL	OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8)
97*4882a593Smuzhiyun #define OMAP5_RNG_CLKCTRL	OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0)
98*4882a593Smuzhiyun #define OMAP5_SHA2MD5_CLKCTRL	OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8)
99*4882a593Smuzhiyun #define OMAP5_DMA_CRYPTO_CLKCTRL	OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8)
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun /* iva clocks */
102*4882a593Smuzhiyun #define OMAP5_IVA_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
103*4882a593Smuzhiyun #define OMAP5_SL2IF_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x28)
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun /* dss clocks */
106*4882a593Smuzhiyun #define OMAP5_DSS_CORE_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun /* gpu clocks */
109*4882a593Smuzhiyun #define OMAP5_GPU_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun /* l3init clocks */
112*4882a593Smuzhiyun #define OMAP5_MMC1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x28)
113*4882a593Smuzhiyun #define OMAP5_MMC2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x30)
114*4882a593Smuzhiyun #define OMAP5_USB_HOST_HS_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x58)
115*4882a593Smuzhiyun #define OMAP5_USB_TLL_HS_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x68)
116*4882a593Smuzhiyun #define OMAP5_SATA_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x88)
117*4882a593Smuzhiyun #define OMAP5_OCP2SCP1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xe0)
118*4882a593Smuzhiyun #define OMAP5_OCP2SCP3_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xe8)
119*4882a593Smuzhiyun #define OMAP5_USB_OTG_SS_CLKCTRL	OMAP5_CLKCTRL_INDEX(0xf0)
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun /* wkupaon clocks */
122*4882a593Smuzhiyun #define OMAP5_L4_WKUP_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x20)
123*4882a593Smuzhiyun #define OMAP5_WD_TIMER2_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x30)
124*4882a593Smuzhiyun #define OMAP5_GPIO1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x38)
125*4882a593Smuzhiyun #define OMAP5_TIMER1_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x40)
126*4882a593Smuzhiyun #define OMAP5_COUNTER_32K_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x50)
127*4882a593Smuzhiyun #define OMAP5_KBD_CLKCTRL	OMAP5_CLKCTRL_INDEX(0x78)
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun #endif
130