1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2017 Texas Instruments, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLK_OMAP4_H 6*4882a593Smuzhiyun #define __DT_BINDINGS_CLK_OMAP4_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define OMAP4_CLKCTRL_OFFSET 0x20 9*4882a593Smuzhiyun #define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET) 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* mpuss clocks */ 12*4882a593Smuzhiyun #define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* tesla clocks */ 15*4882a593Smuzhiyun #define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* abe clocks */ 18*4882a593Smuzhiyun #define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 19*4882a593Smuzhiyun #define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) 20*4882a593Smuzhiyun #define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) 21*4882a593Smuzhiyun #define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) 22*4882a593Smuzhiyun #define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) 23*4882a593Smuzhiyun #define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) 24*4882a593Smuzhiyun #define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) 25*4882a593Smuzhiyun #define OMAP4_MCBSP3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) 26*4882a593Smuzhiyun #define OMAP4_SLIMBUS1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) 27*4882a593Smuzhiyun #define OMAP4_TIMER5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) 28*4882a593Smuzhiyun #define OMAP4_TIMER6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) 29*4882a593Smuzhiyun #define OMAP4_TIMER7_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) 30*4882a593Smuzhiyun #define OMAP4_TIMER8_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) 31*4882a593Smuzhiyun #define OMAP4_WD_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* l4_ao clocks */ 34*4882a593Smuzhiyun #define OMAP4_SMARTREFLEX_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) 35*4882a593Smuzhiyun #define OMAP4_SMARTREFLEX_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) 36*4882a593Smuzhiyun #define OMAP4_SMARTREFLEX_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* l3_1 clocks */ 39*4882a593Smuzhiyun #define OMAP4_L3_MAIN_1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* l3_2 clocks */ 42*4882a593Smuzhiyun #define OMAP4_L3_MAIN_2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 43*4882a593Smuzhiyun #define OMAP4_GPMC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) 44*4882a593Smuzhiyun #define OMAP4_OCMC_RAM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* ducati clocks */ 47*4882a593Smuzhiyun #define OMAP4_IPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* l3_dma clocks */ 50*4882a593Smuzhiyun #define OMAP4_DMA_SYSTEM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* l3_emif clocks */ 53*4882a593Smuzhiyun #define OMAP4_DMM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 54*4882a593Smuzhiyun #define OMAP4_EMIF1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) 55*4882a593Smuzhiyun #define OMAP4_EMIF2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* d2d clocks */ 58*4882a593Smuzhiyun #define OMAP4_C2C_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* l4_cfg clocks */ 61*4882a593Smuzhiyun #define OMAP4_L4_CFG_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 62*4882a593Smuzhiyun #define OMAP4_SPINLOCK_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) 63*4882a593Smuzhiyun #define OMAP4_MAILBOX_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* l3_instr clocks */ 66*4882a593Smuzhiyun #define OMAP4_L3_MAIN_3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 67*4882a593Smuzhiyun #define OMAP4_L3_INSTR_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) 68*4882a593Smuzhiyun #define OMAP4_OCP_WP_NOC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* ivahd clocks */ 71*4882a593Smuzhiyun #define OMAP4_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 72*4882a593Smuzhiyun #define OMAP4_SL2IF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* iss clocks */ 75*4882a593Smuzhiyun #define OMAP4_ISS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 76*4882a593Smuzhiyun #define OMAP4_FDIF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* l3_dss clocks */ 79*4882a593Smuzhiyun #define OMAP4_DSS_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* l3_gfx clocks */ 82*4882a593Smuzhiyun #define OMAP4_GPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* l3_init clocks */ 85*4882a593Smuzhiyun #define OMAP4_MMC1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) 86*4882a593Smuzhiyun #define OMAP4_MMC2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) 87*4882a593Smuzhiyun #define OMAP4_HSI_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) 88*4882a593Smuzhiyun #define OMAP4_USB_HOST_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) 89*4882a593Smuzhiyun #define OMAP4_USB_OTG_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) 90*4882a593Smuzhiyun #define OMAP4_USB_TLL_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) 91*4882a593Smuzhiyun #define OMAP4_USB_HOST_FS_CLKCTRL OMAP4_CLKCTRL_INDEX(0xd0) 92*4882a593Smuzhiyun #define OMAP4_OCP2SCP_USB_PHY_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* l4_per clocks */ 95*4882a593Smuzhiyun #define OMAP4_TIMER10_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) 96*4882a593Smuzhiyun #define OMAP4_TIMER11_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) 97*4882a593Smuzhiyun #define OMAP4_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) 98*4882a593Smuzhiyun #define OMAP4_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) 99*4882a593Smuzhiyun #define OMAP4_TIMER4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) 100*4882a593Smuzhiyun #define OMAP4_TIMER9_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) 101*4882a593Smuzhiyun #define OMAP4_ELM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) 102*4882a593Smuzhiyun #define OMAP4_GPIO2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) 103*4882a593Smuzhiyun #define OMAP4_GPIO3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) 104*4882a593Smuzhiyun #define OMAP4_GPIO4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) 105*4882a593Smuzhiyun #define OMAP4_GPIO5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) 106*4882a593Smuzhiyun #define OMAP4_GPIO6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) 107*4882a593Smuzhiyun #define OMAP4_HDQ1W_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) 108*4882a593Smuzhiyun #define OMAP4_I2C1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa0) 109*4882a593Smuzhiyun #define OMAP4_I2C2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa8) 110*4882a593Smuzhiyun #define OMAP4_I2C3_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb0) 111*4882a593Smuzhiyun #define OMAP4_I2C4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb8) 112*4882a593Smuzhiyun #define OMAP4_L4_PER_CLKCTRL OMAP4_CLKCTRL_INDEX(0xc0) 113*4882a593Smuzhiyun #define OMAP4_MCBSP4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) 114*4882a593Smuzhiyun #define OMAP4_MCSPI1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf0) 115*4882a593Smuzhiyun #define OMAP4_MCSPI2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf8) 116*4882a593Smuzhiyun #define OMAP4_MCSPI3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x100) 117*4882a593Smuzhiyun #define OMAP4_MCSPI4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x108) 118*4882a593Smuzhiyun #define OMAP4_MMC3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x120) 119*4882a593Smuzhiyun #define OMAP4_MMC4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x128) 120*4882a593Smuzhiyun #define OMAP4_SLIMBUS2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x138) 121*4882a593Smuzhiyun #define OMAP4_UART1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x140) 122*4882a593Smuzhiyun #define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148) 123*4882a593Smuzhiyun #define OMAP4_UART3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x150) 124*4882a593Smuzhiyun #define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158) 125*4882a593Smuzhiyun #define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160) 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* l4_secure clocks */ 128*4882a593Smuzhiyun #define OMAP4_L4_SECURE_CLKCTRL_OFFSET 0x1a0 129*4882a593Smuzhiyun #define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP4_L4_SECURE_CLKCTRL_OFFSET) 130*4882a593Smuzhiyun #define OMAP4_AES1_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a0) 131*4882a593Smuzhiyun #define OMAP4_AES2_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a8) 132*4882a593Smuzhiyun #define OMAP4_DES3DES_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b0) 133*4882a593Smuzhiyun #define OMAP4_PKA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b8) 134*4882a593Smuzhiyun #define OMAP4_RNG_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c0) 135*4882a593Smuzhiyun #define OMAP4_SHA2MD5_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c8) 136*4882a593Smuzhiyun #define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1d8) 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* l4_wkup clocks */ 139*4882a593Smuzhiyun #define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 140*4882a593Smuzhiyun #define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) 141*4882a593Smuzhiyun #define OMAP4_GPIO1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) 142*4882a593Smuzhiyun #define OMAP4_TIMER1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) 143*4882a593Smuzhiyun #define OMAP4_COUNTER_32K_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) 144*4882a593Smuzhiyun #define OMAP4_KBD_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* emu_sys clocks */ 147*4882a593Smuzhiyun #define OMAP4_DEBUGSS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #endif 150