1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Nuvoton NPCM7xx Clock Generator binding 4*4882a593Smuzhiyun * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H 11*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_NPCM7XX_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define NPCM7XX_CLK_CPU 0 15*4882a593Smuzhiyun #define NPCM7XX_CLK_GFX_PIXEL 1 16*4882a593Smuzhiyun #define NPCM7XX_CLK_MC 2 17*4882a593Smuzhiyun #define NPCM7XX_CLK_ADC 3 18*4882a593Smuzhiyun #define NPCM7XX_CLK_AHB 4 19*4882a593Smuzhiyun #define NPCM7XX_CLK_TIMER 5 20*4882a593Smuzhiyun #define NPCM7XX_CLK_UART 6 21*4882a593Smuzhiyun #define NPCM7XX_CLK_MMC 7 22*4882a593Smuzhiyun #define NPCM7XX_CLK_SPI3 8 23*4882a593Smuzhiyun #define NPCM7XX_CLK_PCI 9 24*4882a593Smuzhiyun #define NPCM7XX_CLK_AXI 10 25*4882a593Smuzhiyun #define NPCM7XX_CLK_APB4 11 26*4882a593Smuzhiyun #define NPCM7XX_CLK_APB3 12 27*4882a593Smuzhiyun #define NPCM7XX_CLK_APB2 13 28*4882a593Smuzhiyun #define NPCM7XX_CLK_APB1 14 29*4882a593Smuzhiyun #define NPCM7XX_CLK_APB5 15 30*4882a593Smuzhiyun #define NPCM7XX_CLK_CLKOUT 16 31*4882a593Smuzhiyun #define NPCM7XX_CLK_GFX 17 32*4882a593Smuzhiyun #define NPCM7XX_CLK_SU 18 33*4882a593Smuzhiyun #define NPCM7XX_CLK_SU48 19 34*4882a593Smuzhiyun #define NPCM7XX_CLK_SDHC 20 35*4882a593Smuzhiyun #define NPCM7XX_CLK_SPI0 21 36*4882a593Smuzhiyun #define NPCM7XX_CLK_SPIX 22 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define NPCM7XX_CLK_REFCLK 23 39*4882a593Smuzhiyun #define NPCM7XX_CLK_SYSBYPCK 24 40*4882a593Smuzhiyun #define NPCM7XX_CLK_MCBYPCK 25 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define NPCM7XX_NUM_CLOCKS (NPCM7XX_CLK_MCBYPCK+1) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #endif 45