1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2020 MediaTek Inc. 4*4882a593Smuzhiyun * Copyright (c) 2020 BayLibre, SAS. 5*4882a593Smuzhiyun * Author: James Liao <jamesjj.liao@mediatek.com> 6*4882a593Smuzhiyun * Fabien Parent <fparent@baylibre.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MT8167_H 10*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MT8167_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* MT8167 is based on MT8516 */ 13*4882a593Smuzhiyun #include <dt-bindings/clock/mt8516-clk.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* APMIXEDSYS */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define CLK_APMIXED_TVDPLL (CLK_APMIXED_NR_CLK + 0) 18*4882a593Smuzhiyun #define CLK_APMIXED_LVDSPLL (CLK_APMIXED_NR_CLK + 1) 19*4882a593Smuzhiyun #define CLK_APMIXED_HDMI_REF (CLK_APMIXED_NR_CLK + 2) 20*4882a593Smuzhiyun #define MT8167_CLK_APMIXED_NR_CLK (CLK_APMIXED_NR_CLK + 3) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* TOPCKGEN */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define CLK_TOP_DSI0_LNTC_DSICK (CLK_TOP_NR_CLK + 0) 25*4882a593Smuzhiyun #define CLK_TOP_VPLL_DPIX (CLK_TOP_NR_CLK + 1) 26*4882a593Smuzhiyun #define CLK_TOP_LVDSTX_CLKDIG_CTS (CLK_TOP_NR_CLK + 2) 27*4882a593Smuzhiyun #define CLK_TOP_HDMTX_CLKDIG_CTS (CLK_TOP_NR_CLK + 3) 28*4882a593Smuzhiyun #define CLK_TOP_LVDSPLL (CLK_TOP_NR_CLK + 4) 29*4882a593Smuzhiyun #define CLK_TOP_LVDSPLL_D2 (CLK_TOP_NR_CLK + 5) 30*4882a593Smuzhiyun #define CLK_TOP_LVDSPLL_D4 (CLK_TOP_NR_CLK + 6) 31*4882a593Smuzhiyun #define CLK_TOP_LVDSPLL_D8 (CLK_TOP_NR_CLK + 7) 32*4882a593Smuzhiyun #define CLK_TOP_MIPI_26M (CLK_TOP_NR_CLK + 8) 33*4882a593Smuzhiyun #define CLK_TOP_TVDPLL (CLK_TOP_NR_CLK + 9) 34*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D2 (CLK_TOP_NR_CLK + 10) 35*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D4 (CLK_TOP_NR_CLK + 11) 36*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D8 (CLK_TOP_NR_CLK + 12) 37*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D16 (CLK_TOP_NR_CLK + 13) 38*4882a593Smuzhiyun #define CLK_TOP_PWM_MM (CLK_TOP_NR_CLK + 14) 39*4882a593Smuzhiyun #define CLK_TOP_CAM_MM (CLK_TOP_NR_CLK + 15) 40*4882a593Smuzhiyun #define CLK_TOP_MFG_MM (CLK_TOP_NR_CLK + 16) 41*4882a593Smuzhiyun #define CLK_TOP_SPM_52M (CLK_TOP_NR_CLK + 17) 42*4882a593Smuzhiyun #define CLK_TOP_MIPI_26M_DBG (CLK_TOP_NR_CLK + 18) 43*4882a593Smuzhiyun #define CLK_TOP_SCAM_MM (CLK_TOP_NR_CLK + 19) 44*4882a593Smuzhiyun #define CLK_TOP_SMI_MM (CLK_TOP_NR_CLK + 20) 45*4882a593Smuzhiyun #define CLK_TOP_26M_HDMI_SIFM (CLK_TOP_NR_CLK + 21) 46*4882a593Smuzhiyun #define CLK_TOP_26M_CEC (CLK_TOP_NR_CLK + 22) 47*4882a593Smuzhiyun #define CLK_TOP_32K_CEC (CLK_TOP_NR_CLK + 23) 48*4882a593Smuzhiyun #define CLK_TOP_GCPU_B (CLK_TOP_NR_CLK + 24) 49*4882a593Smuzhiyun #define CLK_TOP_RG_VDEC (CLK_TOP_NR_CLK + 25) 50*4882a593Smuzhiyun #define CLK_TOP_RG_FDPI0 (CLK_TOP_NR_CLK + 26) 51*4882a593Smuzhiyun #define CLK_TOP_RG_FDPI1 (CLK_TOP_NR_CLK + 27) 52*4882a593Smuzhiyun #define CLK_TOP_RG_AXI_MFG (CLK_TOP_NR_CLK + 28) 53*4882a593Smuzhiyun #define CLK_TOP_RG_SLOW_MFG (CLK_TOP_NR_CLK + 29) 54*4882a593Smuzhiyun #define CLK_TOP_GFMUX_EMI1X_SEL (CLK_TOP_NR_CLK + 30) 55*4882a593Smuzhiyun #define CLK_TOP_CSW_MUX_MFG_SEL (CLK_TOP_NR_CLK + 31) 56*4882a593Smuzhiyun #define CLK_TOP_CAMTG_MM_SEL (CLK_TOP_NR_CLK + 32) 57*4882a593Smuzhiyun #define CLK_TOP_PWM_MM_SEL (CLK_TOP_NR_CLK + 33) 58*4882a593Smuzhiyun #define CLK_TOP_SPM_52M_SEL (CLK_TOP_NR_CLK + 34) 59*4882a593Smuzhiyun #define CLK_TOP_MFG_MM_SEL (CLK_TOP_NR_CLK + 35) 60*4882a593Smuzhiyun #define CLK_TOP_SMI_MM_SEL (CLK_TOP_NR_CLK + 36) 61*4882a593Smuzhiyun #define CLK_TOP_SCAM_MM_SEL (CLK_TOP_NR_CLK + 37) 62*4882a593Smuzhiyun #define CLK_TOP_VDEC_MM_SEL (CLK_TOP_NR_CLK + 38) 63*4882a593Smuzhiyun #define CLK_TOP_DPI0_MM_SEL (CLK_TOP_NR_CLK + 39) 64*4882a593Smuzhiyun #define CLK_TOP_DPI1_MM_SEL (CLK_TOP_NR_CLK + 40) 65*4882a593Smuzhiyun #define CLK_TOP_AXI_MFG_IN_SEL (CLK_TOP_NR_CLK + 41) 66*4882a593Smuzhiyun #define CLK_TOP_SLOW_MFG_SEL (CLK_TOP_NR_CLK + 42) 67*4882a593Smuzhiyun #define MT8167_CLK_TOP_NR_CLK (CLK_TOP_NR_CLK + 43) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* MFGCFG */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define CLK_MFG_BAXI 0 72*4882a593Smuzhiyun #define CLK_MFG_BMEM 1 73*4882a593Smuzhiyun #define CLK_MFG_BG3D 2 74*4882a593Smuzhiyun #define CLK_MFG_B26M 3 75*4882a593Smuzhiyun #define CLK_MFG_NR_CLK 4 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* MMSYS */ 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define CLK_MM_SMI_COMMON 0 80*4882a593Smuzhiyun #define CLK_MM_SMI_LARB0 1 81*4882a593Smuzhiyun #define CLK_MM_CAM_MDP 2 82*4882a593Smuzhiyun #define CLK_MM_MDP_RDMA 3 83*4882a593Smuzhiyun #define CLK_MM_MDP_RSZ0 4 84*4882a593Smuzhiyun #define CLK_MM_MDP_RSZ1 5 85*4882a593Smuzhiyun #define CLK_MM_MDP_TDSHP 6 86*4882a593Smuzhiyun #define CLK_MM_MDP_WDMA 7 87*4882a593Smuzhiyun #define CLK_MM_MDP_WROT 8 88*4882a593Smuzhiyun #define CLK_MM_FAKE_ENG 9 89*4882a593Smuzhiyun #define CLK_MM_DISP_OVL0 10 90*4882a593Smuzhiyun #define CLK_MM_DISP_RDMA0 11 91*4882a593Smuzhiyun #define CLK_MM_DISP_RDMA1 12 92*4882a593Smuzhiyun #define CLK_MM_DISP_WDMA 13 93*4882a593Smuzhiyun #define CLK_MM_DISP_COLOR 14 94*4882a593Smuzhiyun #define CLK_MM_DISP_CCORR 15 95*4882a593Smuzhiyun #define CLK_MM_DISP_AAL 16 96*4882a593Smuzhiyun #define CLK_MM_DISP_GAMMA 17 97*4882a593Smuzhiyun #define CLK_MM_DISP_DITHER 18 98*4882a593Smuzhiyun #define CLK_MM_DISP_UFOE 19 99*4882a593Smuzhiyun #define CLK_MM_DISP_PWM_MM 20 100*4882a593Smuzhiyun #define CLK_MM_DISP_PWM_26M 21 101*4882a593Smuzhiyun #define CLK_MM_DSI_ENGINE 22 102*4882a593Smuzhiyun #define CLK_MM_DSI_DIGITAL 23 103*4882a593Smuzhiyun #define CLK_MM_DPI0_ENGINE 24 104*4882a593Smuzhiyun #define CLK_MM_DPI0_PXL 25 105*4882a593Smuzhiyun #define CLK_MM_LVDS_PXL 26 106*4882a593Smuzhiyun #define CLK_MM_LVDS_CTS 27 107*4882a593Smuzhiyun #define CLK_MM_DPI1_ENGINE 28 108*4882a593Smuzhiyun #define CLK_MM_DPI1_PXL 29 109*4882a593Smuzhiyun #define CLK_MM_HDMI_PXL 30 110*4882a593Smuzhiyun #define CLK_MM_HDMI_SPDIF 31 111*4882a593Smuzhiyun #define CLK_MM_HDMI_ADSP_BCK 32 112*4882a593Smuzhiyun #define CLK_MM_HDMI_PLL 33 113*4882a593Smuzhiyun #define CLK_MM_NR_CLK 34 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* IMGSYS */ 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define CLK_IMG_LARB1_SMI 0 118*4882a593Smuzhiyun #define CLK_IMG_CAM_SMI 1 119*4882a593Smuzhiyun #define CLK_IMG_CAM_CAM 2 120*4882a593Smuzhiyun #define CLK_IMG_SEN_TG 3 121*4882a593Smuzhiyun #define CLK_IMG_SEN_CAM 4 122*4882a593Smuzhiyun #define CLK_IMG_VENC 5 123*4882a593Smuzhiyun #define CLK_IMG_NR_CLK 6 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* VDECSYS */ 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define CLK_VDEC_CKEN 0 128*4882a593Smuzhiyun #define CLK_VDEC_LARB1_CKEN 1 129*4882a593Smuzhiyun #define CLK_VDEC_NR_CLK 2 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLK_MT8167_H */ 132