1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019 MediaTek Inc. 4*4882a593Smuzhiyun * Author: Wendell Lin <wendell.lin@mediatek.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MT6779_H 8*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MT6779_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* TOPCKGEN */ 11*4882a593Smuzhiyun #define CLK_TOP_AXI 1 12*4882a593Smuzhiyun #define CLK_TOP_MM 2 13*4882a593Smuzhiyun #define CLK_TOP_CAM 3 14*4882a593Smuzhiyun #define CLK_TOP_MFG 4 15*4882a593Smuzhiyun #define CLK_TOP_CAMTG 5 16*4882a593Smuzhiyun #define CLK_TOP_UART 6 17*4882a593Smuzhiyun #define CLK_TOP_SPI 7 18*4882a593Smuzhiyun #define CLK_TOP_MSDC50_0_HCLK 8 19*4882a593Smuzhiyun #define CLK_TOP_MSDC50_0 9 20*4882a593Smuzhiyun #define CLK_TOP_MSDC30_1 10 21*4882a593Smuzhiyun #define CLK_TOP_MSDC30_2 11 22*4882a593Smuzhiyun #define CLK_TOP_AUD 12 23*4882a593Smuzhiyun #define CLK_TOP_AUD_INTBUS 13 24*4882a593Smuzhiyun #define CLK_TOP_FPWRAP_ULPOSC 14 25*4882a593Smuzhiyun #define CLK_TOP_SCP 15 26*4882a593Smuzhiyun #define CLK_TOP_ATB 16 27*4882a593Smuzhiyun #define CLK_TOP_SSPM 17 28*4882a593Smuzhiyun #define CLK_TOP_DPI0 18 29*4882a593Smuzhiyun #define CLK_TOP_SCAM 19 30*4882a593Smuzhiyun #define CLK_TOP_AUD_1 20 31*4882a593Smuzhiyun #define CLK_TOP_AUD_2 21 32*4882a593Smuzhiyun #define CLK_TOP_DISP_PWM 22 33*4882a593Smuzhiyun #define CLK_TOP_SSUSB_TOP_XHCI 23 34*4882a593Smuzhiyun #define CLK_TOP_USB_TOP 24 35*4882a593Smuzhiyun #define CLK_TOP_SPM 25 36*4882a593Smuzhiyun #define CLK_TOP_I2C 26 37*4882a593Smuzhiyun #define CLK_TOP_F52M_MFG 27 38*4882a593Smuzhiyun #define CLK_TOP_SENINF 28 39*4882a593Smuzhiyun #define CLK_TOP_DXCC 29 40*4882a593Smuzhiyun #define CLK_TOP_CAMTG2 30 41*4882a593Smuzhiyun #define CLK_TOP_AUD_ENG1 31 42*4882a593Smuzhiyun #define CLK_TOP_AUD_ENG2 32 43*4882a593Smuzhiyun #define CLK_TOP_FAES_UFSFDE 33 44*4882a593Smuzhiyun #define CLK_TOP_FUFS 34 45*4882a593Smuzhiyun #define CLK_TOP_IMG 35 46*4882a593Smuzhiyun #define CLK_TOP_DSP 36 47*4882a593Smuzhiyun #define CLK_TOP_DSP1 37 48*4882a593Smuzhiyun #define CLK_TOP_DSP2 38 49*4882a593Smuzhiyun #define CLK_TOP_IPU_IF 39 50*4882a593Smuzhiyun #define CLK_TOP_CAMTG3 40 51*4882a593Smuzhiyun #define CLK_TOP_CAMTG4 41 52*4882a593Smuzhiyun #define CLK_TOP_PMICSPI 42 53*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_CK 43 54*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D2 44 55*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D3 45 56*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D5 46 57*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D7 47 58*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D2_D2 48 59*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D2_D4 49 60*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D2_D8 50 61*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D2_D16 51 62*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D3_D2 52 63*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D3_D4 53 64*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D3_D8 54 65*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D5_D2 55 66*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D5_D4 56 67*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D7_D2 57 68*4882a593Smuzhiyun #define CLK_TOP_MAINPLL_D7_D4 58 69*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_CK 59 70*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D2 60 71*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D3 61 72*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D5 62 73*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D7 63 74*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D2_D2 64 75*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D2_D4 65 76*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D2_D8 66 77*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D3_D2 67 78*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D3_D4 68 79*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D3_D8 69 80*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D5_D2 70 81*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D5_D4 71 82*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D5_D8 72 83*4882a593Smuzhiyun #define CLK_TOP_APLL1_CK 73 84*4882a593Smuzhiyun #define CLK_TOP_APLL1_D2 74 85*4882a593Smuzhiyun #define CLK_TOP_APLL1_D4 75 86*4882a593Smuzhiyun #define CLK_TOP_APLL1_D8 76 87*4882a593Smuzhiyun #define CLK_TOP_APLL2_CK 77 88*4882a593Smuzhiyun #define CLK_TOP_APLL2_D2 78 89*4882a593Smuzhiyun #define CLK_TOP_APLL2_D4 79 90*4882a593Smuzhiyun #define CLK_TOP_APLL2_D8 80 91*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_CK 81 92*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D2 82 93*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D4 83 94*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D8 84 95*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_D16 85 96*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_CK 86 97*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_D2 87 98*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_D4 88 99*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_D8 89 100*4882a593Smuzhiyun #define CLK_TOP_MSDCPLL_D16 90 101*4882a593Smuzhiyun #define CLK_TOP_AD_OSC_CK 91 102*4882a593Smuzhiyun #define CLK_TOP_OSC_D2 92 103*4882a593Smuzhiyun #define CLK_TOP_OSC_D4 93 104*4882a593Smuzhiyun #define CLK_TOP_OSC_D8 94 105*4882a593Smuzhiyun #define CLK_TOP_OSC_D16 95 106*4882a593Smuzhiyun #define CLK_TOP_F26M_CK_D2 96 107*4882a593Smuzhiyun #define CLK_TOP_MFGPLL_CK 97 108*4882a593Smuzhiyun #define CLK_TOP_UNIVP_192M_CK 98 109*4882a593Smuzhiyun #define CLK_TOP_UNIVP_192M_D2 99 110*4882a593Smuzhiyun #define CLK_TOP_UNIVP_192M_D4 100 111*4882a593Smuzhiyun #define CLK_TOP_UNIVP_192M_D8 101 112*4882a593Smuzhiyun #define CLK_TOP_UNIVP_192M_D16 102 113*4882a593Smuzhiyun #define CLK_TOP_UNIVP_192M_D32 103 114*4882a593Smuzhiyun #define CLK_TOP_MMPLL_CK 104 115*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D4 105 116*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D4_D2 106 117*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D4_D4 107 118*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D5 108 119*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D5_D2 109 120*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D5_D4 110 121*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D6 111 122*4882a593Smuzhiyun #define CLK_TOP_MMPLL_D7 112 123*4882a593Smuzhiyun #define CLK_TOP_CLK26M 113 124*4882a593Smuzhiyun #define CLK_TOP_CLK13M 114 125*4882a593Smuzhiyun #define CLK_TOP_ADSP 115 126*4882a593Smuzhiyun #define CLK_TOP_DPMAIF 116 127*4882a593Smuzhiyun #define CLK_TOP_VENC 117 128*4882a593Smuzhiyun #define CLK_TOP_VDEC 118 129*4882a593Smuzhiyun #define CLK_TOP_CAMTM 119 130*4882a593Smuzhiyun #define CLK_TOP_PWM 120 131*4882a593Smuzhiyun #define CLK_TOP_ADSPPLL_CK 121 132*4882a593Smuzhiyun #define CLK_TOP_I2S0_M_SEL 122 133*4882a593Smuzhiyun #define CLK_TOP_I2S1_M_SEL 123 134*4882a593Smuzhiyun #define CLK_TOP_I2S2_M_SEL 124 135*4882a593Smuzhiyun #define CLK_TOP_I2S3_M_SEL 125 136*4882a593Smuzhiyun #define CLK_TOP_I2S4_M_SEL 126 137*4882a593Smuzhiyun #define CLK_TOP_I2S5_M_SEL 127 138*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV0 128 139*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV1 129 140*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV2 130 141*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV3 131 142*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV4 132 143*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIVB 133 144*4882a593Smuzhiyun #define CLK_TOP_APLL12_DIV5 134 145*4882a593Smuzhiyun #define CLK_TOP_IPE 135 146*4882a593Smuzhiyun #define CLK_TOP_DPE 136 147*4882a593Smuzhiyun #define CLK_TOP_CCU 137 148*4882a593Smuzhiyun #define CLK_TOP_DSP3 138 149*4882a593Smuzhiyun #define CLK_TOP_SENINF1 139 150*4882a593Smuzhiyun #define CLK_TOP_SENINF2 140 151*4882a593Smuzhiyun #define CLK_TOP_AUD_H 141 152*4882a593Smuzhiyun #define CLK_TOP_CAMTG5 142 153*4882a593Smuzhiyun #define CLK_TOP_TVDPLL_MAINPLL_D2_CK 143 154*4882a593Smuzhiyun #define CLK_TOP_AD_OSC2_CK 144 155*4882a593Smuzhiyun #define CLK_TOP_OSC2_D2 145 156*4882a593Smuzhiyun #define CLK_TOP_OSC2_D3 146 157*4882a593Smuzhiyun #define CLK_TOP_FMEM_466M_CK 147 158*4882a593Smuzhiyun #define CLK_TOP_ADSPPLL_D4 148 159*4882a593Smuzhiyun #define CLK_TOP_ADSPPLL_D5 149 160*4882a593Smuzhiyun #define CLK_TOP_ADSPPLL_D6 150 161*4882a593Smuzhiyun #define CLK_TOP_OSC_D10 151 162*4882a593Smuzhiyun #define CLK_TOP_UNIVPLL_D3_D16 152 163*4882a593Smuzhiyun #define CLK_TOP_NR_CLK 153 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun /* APMIXED */ 166*4882a593Smuzhiyun #define CLK_APMIXED_ARMPLL_LL 1 167*4882a593Smuzhiyun #define CLK_APMIXED_ARMPLL_BL 2 168*4882a593Smuzhiyun #define CLK_APMIXED_ARMPLL_BB 3 169*4882a593Smuzhiyun #define CLK_APMIXED_CCIPLL 4 170*4882a593Smuzhiyun #define CLK_APMIXED_MAINPLL 5 171*4882a593Smuzhiyun #define CLK_APMIXED_UNIV2PLL 6 172*4882a593Smuzhiyun #define CLK_APMIXED_MSDCPLL 7 173*4882a593Smuzhiyun #define CLK_APMIXED_ADSPPLL 8 174*4882a593Smuzhiyun #define CLK_APMIXED_MMPLL 9 175*4882a593Smuzhiyun #define CLK_APMIXED_MFGPLL 10 176*4882a593Smuzhiyun #define CLK_APMIXED_TVDPLL 11 177*4882a593Smuzhiyun #define CLK_APMIXED_APLL1 12 178*4882a593Smuzhiyun #define CLK_APMIXED_APLL2 13 179*4882a593Smuzhiyun #define CLK_APMIXED_SSUSB26M 14 180*4882a593Smuzhiyun #define CLK_APMIXED_APPLL26M 15 181*4882a593Smuzhiyun #define CLK_APMIXED_MIPIC0_26M 16 182*4882a593Smuzhiyun #define CLK_APMIXED_MDPLLGP26M 17 183*4882a593Smuzhiyun #define CLK_APMIXED_MM_F26M 18 184*4882a593Smuzhiyun #define CLK_APMIXED_UFS26M 19 185*4882a593Smuzhiyun #define CLK_APMIXED_MIPIC1_26M 20 186*4882a593Smuzhiyun #define CLK_APMIXED_MEMPLL26M 21 187*4882a593Smuzhiyun #define CLK_APMIXED_CLKSQ_LVPLL_26M 22 188*4882a593Smuzhiyun #define CLK_APMIXED_MIPID0_26M 23 189*4882a593Smuzhiyun #define CLK_APMIXED_MIPID1_26M 24 190*4882a593Smuzhiyun #define CLK_APMIXED_NR_CLK 25 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun /* CAMSYS */ 193*4882a593Smuzhiyun #define CLK_CAM_LARB10 1 194*4882a593Smuzhiyun #define CLK_CAM_DFP_VAD 2 195*4882a593Smuzhiyun #define CLK_CAM_LARB11 3 196*4882a593Smuzhiyun #define CLK_CAM_LARB9 4 197*4882a593Smuzhiyun #define CLK_CAM_CAM 5 198*4882a593Smuzhiyun #define CLK_CAM_CAMTG 6 199*4882a593Smuzhiyun #define CLK_CAM_SENINF 7 200*4882a593Smuzhiyun #define CLK_CAM_CAMSV0 8 201*4882a593Smuzhiyun #define CLK_CAM_CAMSV1 9 202*4882a593Smuzhiyun #define CLK_CAM_CAMSV2 10 203*4882a593Smuzhiyun #define CLK_CAM_CAMSV3 11 204*4882a593Smuzhiyun #define CLK_CAM_CCU 12 205*4882a593Smuzhiyun #define CLK_CAM_FAKE_ENG 13 206*4882a593Smuzhiyun #define CLK_CAM_NR_CLK 14 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun /* INFRA */ 209*4882a593Smuzhiyun #define CLK_INFRA_PMIC_TMR 1 210*4882a593Smuzhiyun #define CLK_INFRA_PMIC_AP 2 211*4882a593Smuzhiyun #define CLK_INFRA_PMIC_MD 3 212*4882a593Smuzhiyun #define CLK_INFRA_PMIC_CONN 4 213*4882a593Smuzhiyun #define CLK_INFRA_SCPSYS 5 214*4882a593Smuzhiyun #define CLK_INFRA_SEJ 6 215*4882a593Smuzhiyun #define CLK_INFRA_APXGPT 7 216*4882a593Smuzhiyun #define CLK_INFRA_ICUSB 8 217*4882a593Smuzhiyun #define CLK_INFRA_GCE 9 218*4882a593Smuzhiyun #define CLK_INFRA_THERM 10 219*4882a593Smuzhiyun #define CLK_INFRA_I2C0 11 220*4882a593Smuzhiyun #define CLK_INFRA_I2C1 12 221*4882a593Smuzhiyun #define CLK_INFRA_I2C2 13 222*4882a593Smuzhiyun #define CLK_INFRA_I2C3 14 223*4882a593Smuzhiyun #define CLK_INFRA_PWM_HCLK 15 224*4882a593Smuzhiyun #define CLK_INFRA_PWM1 16 225*4882a593Smuzhiyun #define CLK_INFRA_PWM2 17 226*4882a593Smuzhiyun #define CLK_INFRA_PWM3 18 227*4882a593Smuzhiyun #define CLK_INFRA_PWM4 19 228*4882a593Smuzhiyun #define CLK_INFRA_PWM 20 229*4882a593Smuzhiyun #define CLK_INFRA_UART0 21 230*4882a593Smuzhiyun #define CLK_INFRA_UART1 22 231*4882a593Smuzhiyun #define CLK_INFRA_UART2 23 232*4882a593Smuzhiyun #define CLK_INFRA_UART3 24 233*4882a593Smuzhiyun #define CLK_INFRA_GCE_26M 25 234*4882a593Smuzhiyun #define CLK_INFRA_CQ_DMA_FPC 26 235*4882a593Smuzhiyun #define CLK_INFRA_BTIF 27 236*4882a593Smuzhiyun #define CLK_INFRA_SPI0 28 237*4882a593Smuzhiyun #define CLK_INFRA_MSDC0 29 238*4882a593Smuzhiyun #define CLK_INFRA_MSDC1 30 239*4882a593Smuzhiyun #define CLK_INFRA_MSDC2 31 240*4882a593Smuzhiyun #define CLK_INFRA_MSDC0_SCK 32 241*4882a593Smuzhiyun #define CLK_INFRA_DVFSRC 33 242*4882a593Smuzhiyun #define CLK_INFRA_GCPU 34 243*4882a593Smuzhiyun #define CLK_INFRA_TRNG 35 244*4882a593Smuzhiyun #define CLK_INFRA_AUXADC 36 245*4882a593Smuzhiyun #define CLK_INFRA_CPUM 37 246*4882a593Smuzhiyun #define CLK_INFRA_CCIF1_AP 38 247*4882a593Smuzhiyun #define CLK_INFRA_CCIF1_MD 39 248*4882a593Smuzhiyun #define CLK_INFRA_AUXADC_MD 40 249*4882a593Smuzhiyun #define CLK_INFRA_MSDC1_SCK 41 250*4882a593Smuzhiyun #define CLK_INFRA_MSDC2_SCK 42 251*4882a593Smuzhiyun #define CLK_INFRA_AP_DMA 43 252*4882a593Smuzhiyun #define CLK_INFRA_XIU 44 253*4882a593Smuzhiyun #define CLK_INFRA_DEVICE_APC 45 254*4882a593Smuzhiyun #define CLK_INFRA_CCIF_AP 46 255*4882a593Smuzhiyun #define CLK_INFRA_DEBUGSYS 47 256*4882a593Smuzhiyun #define CLK_INFRA_AUD 48 257*4882a593Smuzhiyun #define CLK_INFRA_CCIF_MD 49 258*4882a593Smuzhiyun #define CLK_INFRA_DXCC_SEC_CORE 50 259*4882a593Smuzhiyun #define CLK_INFRA_DXCC_AO 51 260*4882a593Smuzhiyun #define CLK_INFRA_DRAMC_F26M 52 261*4882a593Smuzhiyun #define CLK_INFRA_IRTX 53 262*4882a593Smuzhiyun #define CLK_INFRA_DISP_PWM 54 263*4882a593Smuzhiyun #define CLK_INFRA_DPMAIF_CK 55 264*4882a593Smuzhiyun #define CLK_INFRA_AUD_26M_BCLK 56 265*4882a593Smuzhiyun #define CLK_INFRA_SPI1 57 266*4882a593Smuzhiyun #define CLK_INFRA_I2C4 58 267*4882a593Smuzhiyun #define CLK_INFRA_MODEM_TEMP_SHARE 59 268*4882a593Smuzhiyun #define CLK_INFRA_SPI2 60 269*4882a593Smuzhiyun #define CLK_INFRA_SPI3 61 270*4882a593Smuzhiyun #define CLK_INFRA_UNIPRO_SCK 62 271*4882a593Smuzhiyun #define CLK_INFRA_UNIPRO_TICK 63 272*4882a593Smuzhiyun #define CLK_INFRA_UFS_MP_SAP_BCLK 64 273*4882a593Smuzhiyun #define CLK_INFRA_MD32_BCLK 65 274*4882a593Smuzhiyun #define CLK_INFRA_SSPM 66 275*4882a593Smuzhiyun #define CLK_INFRA_UNIPRO_MBIST 67 276*4882a593Smuzhiyun #define CLK_INFRA_SSPM_BUS_HCLK 68 277*4882a593Smuzhiyun #define CLK_INFRA_I2C5 69 278*4882a593Smuzhiyun #define CLK_INFRA_I2C5_ARBITER 70 279*4882a593Smuzhiyun #define CLK_INFRA_I2C5_IMM 71 280*4882a593Smuzhiyun #define CLK_INFRA_I2C1_ARBITER 72 281*4882a593Smuzhiyun #define CLK_INFRA_I2C1_IMM 73 282*4882a593Smuzhiyun #define CLK_INFRA_I2C2_ARBITER 74 283*4882a593Smuzhiyun #define CLK_INFRA_I2C2_IMM 75 284*4882a593Smuzhiyun #define CLK_INFRA_SPI4 76 285*4882a593Smuzhiyun #define CLK_INFRA_SPI5 77 286*4882a593Smuzhiyun #define CLK_INFRA_CQ_DMA 78 287*4882a593Smuzhiyun #define CLK_INFRA_UFS 79 288*4882a593Smuzhiyun #define CLK_INFRA_AES_UFSFDE 80 289*4882a593Smuzhiyun #define CLK_INFRA_UFS_TICK 81 290*4882a593Smuzhiyun #define CLK_INFRA_MSDC0_SELF 82 291*4882a593Smuzhiyun #define CLK_INFRA_MSDC1_SELF 83 292*4882a593Smuzhiyun #define CLK_INFRA_MSDC2_SELF 84 293*4882a593Smuzhiyun #define CLK_INFRA_SSPM_26M_SELF 85 294*4882a593Smuzhiyun #define CLK_INFRA_SSPM_32K_SELF 86 295*4882a593Smuzhiyun #define CLK_INFRA_UFS_AXI 87 296*4882a593Smuzhiyun #define CLK_INFRA_I2C6 88 297*4882a593Smuzhiyun #define CLK_INFRA_AP_MSDC0 89 298*4882a593Smuzhiyun #define CLK_INFRA_MD_MSDC0 90 299*4882a593Smuzhiyun #define CLK_INFRA_USB 91 300*4882a593Smuzhiyun #define CLK_INFRA_DEVMPU_BCLK 92 301*4882a593Smuzhiyun #define CLK_INFRA_CCIF2_AP 93 302*4882a593Smuzhiyun #define CLK_INFRA_CCIF2_MD 94 303*4882a593Smuzhiyun #define CLK_INFRA_CCIF3_AP 95 304*4882a593Smuzhiyun #define CLK_INFRA_CCIF3_MD 96 305*4882a593Smuzhiyun #define CLK_INFRA_SEJ_F13M 97 306*4882a593Smuzhiyun #define CLK_INFRA_AES_BCLK 98 307*4882a593Smuzhiyun #define CLK_INFRA_I2C7 99 308*4882a593Smuzhiyun #define CLK_INFRA_I2C8 100 309*4882a593Smuzhiyun #define CLK_INFRA_FBIST2FPC 101 310*4882a593Smuzhiyun #define CLK_INFRA_CCIF4_AP 102 311*4882a593Smuzhiyun #define CLK_INFRA_CCIF4_MD 103 312*4882a593Smuzhiyun #define CLK_INFRA_FADSP 104 313*4882a593Smuzhiyun #define CLK_INFRA_SSUSB_XHCI 105 314*4882a593Smuzhiyun #define CLK_INFRA_SPI6 106 315*4882a593Smuzhiyun #define CLK_INFRA_SPI7 107 316*4882a593Smuzhiyun #define CLK_INFRA_NR_CLK 108 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun /* MFGCFG */ 319*4882a593Smuzhiyun #define CLK_MFGCFG_BG3D 1 320*4882a593Smuzhiyun #define CLK_MFGCFG_NR_CLK 2 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun /* IMG */ 323*4882a593Smuzhiyun #define CLK_IMG_WPE_A 1 324*4882a593Smuzhiyun #define CLK_IMG_MFB 2 325*4882a593Smuzhiyun #define CLK_IMG_DIP 3 326*4882a593Smuzhiyun #define CLK_IMG_LARB6 4 327*4882a593Smuzhiyun #define CLK_IMG_LARB5 5 328*4882a593Smuzhiyun #define CLK_IMG_NR_CLK 6 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun /* IPE */ 331*4882a593Smuzhiyun #define CLK_IPE_LARB7 1 332*4882a593Smuzhiyun #define CLK_IPE_LARB8 2 333*4882a593Smuzhiyun #define CLK_IPE_SMI_SUBCOM 3 334*4882a593Smuzhiyun #define CLK_IPE_FD 4 335*4882a593Smuzhiyun #define CLK_IPE_FE 5 336*4882a593Smuzhiyun #define CLK_IPE_RSC 6 337*4882a593Smuzhiyun #define CLK_IPE_DPE 7 338*4882a593Smuzhiyun #define CLK_IPE_NR_CLK 8 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun /* MM_CONFIG */ 341*4882a593Smuzhiyun #define CLK_MM_SMI_COMMON 1 342*4882a593Smuzhiyun #define CLK_MM_SMI_LARB0 2 343*4882a593Smuzhiyun #define CLK_MM_SMI_LARB1 3 344*4882a593Smuzhiyun #define CLK_MM_GALS_COMM0 4 345*4882a593Smuzhiyun #define CLK_MM_GALS_COMM1 5 346*4882a593Smuzhiyun #define CLK_MM_GALS_CCU2MM 6 347*4882a593Smuzhiyun #define CLK_MM_GALS_IPU12MM 7 348*4882a593Smuzhiyun #define CLK_MM_GALS_IMG2MM 8 349*4882a593Smuzhiyun #define CLK_MM_GALS_CAM2MM 9 350*4882a593Smuzhiyun #define CLK_MM_GALS_IPU2MM 10 351*4882a593Smuzhiyun #define CLK_MM_MDP_DL_TXCK 11 352*4882a593Smuzhiyun #define CLK_MM_IPU_DL_TXCK 12 353*4882a593Smuzhiyun #define CLK_MM_MDP_RDMA0 13 354*4882a593Smuzhiyun #define CLK_MM_MDP_RDMA1 14 355*4882a593Smuzhiyun #define CLK_MM_MDP_RSZ0 15 356*4882a593Smuzhiyun #define CLK_MM_MDP_RSZ1 16 357*4882a593Smuzhiyun #define CLK_MM_MDP_TDSHP 17 358*4882a593Smuzhiyun #define CLK_MM_MDP_WROT0 18 359*4882a593Smuzhiyun #define CLK_MM_FAKE_ENG 19 360*4882a593Smuzhiyun #define CLK_MM_DISP_OVL0 20 361*4882a593Smuzhiyun #define CLK_MM_DISP_OVL0_2L 21 362*4882a593Smuzhiyun #define CLK_MM_DISP_OVL1_2L 22 363*4882a593Smuzhiyun #define CLK_MM_DISP_RDMA0 23 364*4882a593Smuzhiyun #define CLK_MM_DISP_RDMA1 24 365*4882a593Smuzhiyun #define CLK_MM_DISP_WDMA0 25 366*4882a593Smuzhiyun #define CLK_MM_DISP_COLOR0 26 367*4882a593Smuzhiyun #define CLK_MM_DISP_CCORR0 27 368*4882a593Smuzhiyun #define CLK_MM_DISP_AAL0 28 369*4882a593Smuzhiyun #define CLK_MM_DISP_GAMMA0 29 370*4882a593Smuzhiyun #define CLK_MM_DISP_DITHER0 30 371*4882a593Smuzhiyun #define CLK_MM_DISP_SPLIT 31 372*4882a593Smuzhiyun #define CLK_MM_DSI0_MM_CK 32 373*4882a593Smuzhiyun #define CLK_MM_DSI0_IF_CK 33 374*4882a593Smuzhiyun #define CLK_MM_DPI_MM_CK 34 375*4882a593Smuzhiyun #define CLK_MM_DPI_IF_CK 35 376*4882a593Smuzhiyun #define CLK_MM_FAKE_ENG2 36 377*4882a593Smuzhiyun #define CLK_MM_MDP_DL_RX_CK 37 378*4882a593Smuzhiyun #define CLK_MM_IPU_DL_RX_CK 38 379*4882a593Smuzhiyun #define CLK_MM_26M 39 380*4882a593Smuzhiyun #define CLK_MM_MM_R2Y 40 381*4882a593Smuzhiyun #define CLK_MM_DISP_RSZ 41 382*4882a593Smuzhiyun #define CLK_MM_MDP_WDMA0 42 383*4882a593Smuzhiyun #define CLK_MM_MDP_AAL 43 384*4882a593Smuzhiyun #define CLK_MM_MDP_HDR 44 385*4882a593Smuzhiyun #define CLK_MM_DBI_MM_CK 45 386*4882a593Smuzhiyun #define CLK_MM_DBI_IF_CK 46 387*4882a593Smuzhiyun #define CLK_MM_MDP_WROT1 47 388*4882a593Smuzhiyun #define CLK_MM_DISP_POSTMASK0 48 389*4882a593Smuzhiyun #define CLK_MM_DISP_HRT_BW 49 390*4882a593Smuzhiyun #define CLK_MM_DISP_OVL_FBDC 50 391*4882a593Smuzhiyun #define CLK_MM_NR_CLK 51 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun /* VDEC_GCON */ 394*4882a593Smuzhiyun #define CLK_VDEC_VDEC 1 395*4882a593Smuzhiyun #define CLK_VDEC_LARB1 2 396*4882a593Smuzhiyun #define CLK_VDEC_GCON_NR_CLK 3 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun /* VENC_GCON */ 399*4882a593Smuzhiyun #define CLK_VENC_GCON_LARB 1 400*4882a593Smuzhiyun #define CLK_VENC_GCON_VENC 2 401*4882a593Smuzhiyun #define CLK_VENC_GCON_JPGENC 3 402*4882a593Smuzhiyun #define CLK_VENC_GCON_GALS 4 403*4882a593Smuzhiyun #define CLK_VENC_GCON_NR_CLK 5 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun /* AUD */ 406*4882a593Smuzhiyun #define CLK_AUD_AFE 1 407*4882a593Smuzhiyun #define CLK_AUD_22M 2 408*4882a593Smuzhiyun #define CLK_AUD_24M 3 409*4882a593Smuzhiyun #define CLK_AUD_APLL2_TUNER 4 410*4882a593Smuzhiyun #define CLK_AUD_APLL_TUNER 5 411*4882a593Smuzhiyun #define CLK_AUD_TDM 6 412*4882a593Smuzhiyun #define CLK_AUD_ADC 7 413*4882a593Smuzhiyun #define CLK_AUD_DAC 8 414*4882a593Smuzhiyun #define CLK_AUD_DAC_PREDIS 9 415*4882a593Smuzhiyun #define CLK_AUD_TML 10 416*4882a593Smuzhiyun #define CLK_AUD_NLE 11 417*4882a593Smuzhiyun #define CLK_AUD_I2S1_BCLK_SW 12 418*4882a593Smuzhiyun #define CLK_AUD_I2S2_BCLK_SW 13 419*4882a593Smuzhiyun #define CLK_AUD_I2S3_BCLK_SW 14 420*4882a593Smuzhiyun #define CLK_AUD_I2S4_BCLK_SW 15 421*4882a593Smuzhiyun #define CLK_AUD_I2S5_BCLK_SW 16 422*4882a593Smuzhiyun #define CLK_AUD_CONN_I2S_ASRC 17 423*4882a593Smuzhiyun #define CLK_AUD_GENERAL1_ASRC 18 424*4882a593Smuzhiyun #define CLK_AUD_GENERAL2_ASRC 19 425*4882a593Smuzhiyun #define CLK_AUD_DAC_HIRES 20 426*4882a593Smuzhiyun #define CLK_AUD_PDN_ADDA6_ADC 21 427*4882a593Smuzhiyun #define CLK_AUD_ADC_HIRES 22 428*4882a593Smuzhiyun #define CLK_AUD_ADC_HIRES_TML 23 429*4882a593Smuzhiyun #define CLK_AUD_ADDA6_ADC_HIRES 24 430*4882a593Smuzhiyun #define CLK_AUD_3RD_DAC 25 431*4882a593Smuzhiyun #define CLK_AUD_3RD_DAC_PREDIS 26 432*4882a593Smuzhiyun #define CLK_AUD_3RD_DAC_TML 27 433*4882a593Smuzhiyun #define CLK_AUD_3RD_DAC_HIRES 28 434*4882a593Smuzhiyun #define CLK_AUD_NR_CLK 29 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLK_MT6779_H */ 437