1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2019 Microchip Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Lars Povlsen <lars.povlsen@microchip.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_SPARX5_H 9*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_SPARX5_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CLK_ID_CORE 0 12*4882a593Smuzhiyun #define CLK_ID_DDR 1 13*4882a593Smuzhiyun #define CLK_ID_CPU2 2 14*4882a593Smuzhiyun #define CLK_ID_ARM2 3 15*4882a593Smuzhiyun #define CLK_ID_AUX1 4 16*4882a593Smuzhiyun #define CLK_ID_AUX2 5 17*4882a593Smuzhiyun #define CLK_ID_AUX3 6 18*4882a593Smuzhiyun #define CLK_ID_AUX4 7 19*4882a593Smuzhiyun #define CLK_ID_SYNCE 8 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define N_CLOCKS 9 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #endif 24