1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Purna Chandra Mandal,<purna.mandal@microchip.com> 4*4882a593Smuzhiyun * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ 8*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* clock output indices */ 11*4882a593Smuzhiyun #define POSCCLK 0 12*4882a593Smuzhiyun #define FRCCLK 1 13*4882a593Smuzhiyun #define BFRCCLK 2 14*4882a593Smuzhiyun #define LPRCCLK 3 15*4882a593Smuzhiyun #define SOSCCLK 4 16*4882a593Smuzhiyun #define FRCDIVCLK 5 17*4882a593Smuzhiyun #define PLLCLK 6 18*4882a593Smuzhiyun #define SCLK 7 19*4882a593Smuzhiyun #define PB1CLK 8 20*4882a593Smuzhiyun #define PB2CLK 9 21*4882a593Smuzhiyun #define PB3CLK 10 22*4882a593Smuzhiyun #define PB4CLK 11 23*4882a593Smuzhiyun #define PB5CLK 12 24*4882a593Smuzhiyun #define PB6CLK 13 25*4882a593Smuzhiyun #define PB7CLK 14 26*4882a593Smuzhiyun #define REF1CLK 15 27*4882a593Smuzhiyun #define REF2CLK 16 28*4882a593Smuzhiyun #define REF3CLK 17 29*4882a593Smuzhiyun #define REF4CLK 18 30*4882a593Smuzhiyun #define REF5CLK 19 31*4882a593Smuzhiyun #define UPLLCLK 20 32*4882a593Smuzhiyun #define MAXCLKS 21 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #endif /* _DT_BINDINGS_CLK_MICROCHIP_PIC32_H_ */ 35