1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Meson8b clock tree IDs 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __MESON8B_CLKC_H 7*4882a593Smuzhiyun #define __MESON8B_CLKC_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define CLKID_UNUSED 0 10*4882a593Smuzhiyun #define CLKID_XTAL 1 11*4882a593Smuzhiyun #define CLKID_PLL_FIXED 2 12*4882a593Smuzhiyun #define CLKID_PLL_VID 3 13*4882a593Smuzhiyun #define CLKID_PLL_SYS 4 14*4882a593Smuzhiyun #define CLKID_FCLK_DIV2 5 15*4882a593Smuzhiyun #define CLKID_FCLK_DIV3 6 16*4882a593Smuzhiyun #define CLKID_FCLK_DIV4 7 17*4882a593Smuzhiyun #define CLKID_FCLK_DIV5 8 18*4882a593Smuzhiyun #define CLKID_FCLK_DIV7 9 19*4882a593Smuzhiyun #define CLKID_CLK81 10 20*4882a593Smuzhiyun #define CLKID_MALI 11 21*4882a593Smuzhiyun #define CLKID_CPUCLK 12 22*4882a593Smuzhiyun #define CLKID_ZERO 13 23*4882a593Smuzhiyun #define CLKID_MPEG_SEL 14 24*4882a593Smuzhiyun #define CLKID_MPEG_DIV 15 25*4882a593Smuzhiyun #define CLKID_DDR 16 26*4882a593Smuzhiyun #define CLKID_DOS 17 27*4882a593Smuzhiyun #define CLKID_ISA 18 28*4882a593Smuzhiyun #define CLKID_PL301 19 29*4882a593Smuzhiyun #define CLKID_PERIPHS 20 30*4882a593Smuzhiyun #define CLKID_SPICC 21 31*4882a593Smuzhiyun #define CLKID_I2C 22 32*4882a593Smuzhiyun #define CLKID_SAR_ADC 23 33*4882a593Smuzhiyun #define CLKID_SMART_CARD 24 34*4882a593Smuzhiyun #define CLKID_RNG0 25 35*4882a593Smuzhiyun #define CLKID_UART0 26 36*4882a593Smuzhiyun #define CLKID_SDHC 27 37*4882a593Smuzhiyun #define CLKID_STREAM 28 38*4882a593Smuzhiyun #define CLKID_ASYNC_FIFO 29 39*4882a593Smuzhiyun #define CLKID_SDIO 30 40*4882a593Smuzhiyun #define CLKID_ABUF 31 41*4882a593Smuzhiyun #define CLKID_HIU_IFACE 32 42*4882a593Smuzhiyun #define CLKID_ASSIST_MISC 33 43*4882a593Smuzhiyun #define CLKID_SPI 34 44*4882a593Smuzhiyun #define CLKID_I2S_SPDIF 35 45*4882a593Smuzhiyun #define CLKID_ETH 36 46*4882a593Smuzhiyun #define CLKID_DEMUX 37 47*4882a593Smuzhiyun #define CLKID_AIU_GLUE 38 48*4882a593Smuzhiyun #define CLKID_IEC958 39 49*4882a593Smuzhiyun #define CLKID_I2S_OUT 40 50*4882a593Smuzhiyun #define CLKID_AMCLK 41 51*4882a593Smuzhiyun #define CLKID_AIFIFO2 42 52*4882a593Smuzhiyun #define CLKID_MIXER 43 53*4882a593Smuzhiyun #define CLKID_MIXER_IFACE 44 54*4882a593Smuzhiyun #define CLKID_ADC 45 55*4882a593Smuzhiyun #define CLKID_BLKMV 46 56*4882a593Smuzhiyun #define CLKID_AIU 47 57*4882a593Smuzhiyun #define CLKID_UART1 48 58*4882a593Smuzhiyun #define CLKID_G2D 49 59*4882a593Smuzhiyun #define CLKID_USB0 50 60*4882a593Smuzhiyun #define CLKID_USB1 51 61*4882a593Smuzhiyun #define CLKID_RESET 52 62*4882a593Smuzhiyun #define CLKID_NAND 53 63*4882a593Smuzhiyun #define CLKID_DOS_PARSER 54 64*4882a593Smuzhiyun #define CLKID_USB 55 65*4882a593Smuzhiyun #define CLKID_VDIN1 56 66*4882a593Smuzhiyun #define CLKID_AHB_ARB0 57 67*4882a593Smuzhiyun #define CLKID_EFUSE 58 68*4882a593Smuzhiyun #define CLKID_BOOT_ROM 59 69*4882a593Smuzhiyun #define CLKID_AHB_DATA_BUS 60 70*4882a593Smuzhiyun #define CLKID_AHB_CTRL_BUS 61 71*4882a593Smuzhiyun #define CLKID_HDMI_INTR_SYNC 62 72*4882a593Smuzhiyun #define CLKID_HDMI_PCLK 63 73*4882a593Smuzhiyun #define CLKID_USB1_DDR_BRIDGE 64 74*4882a593Smuzhiyun #define CLKID_USB0_DDR_BRIDGE 65 75*4882a593Smuzhiyun #define CLKID_MMC_PCLK 66 76*4882a593Smuzhiyun #define CLKID_DVIN 67 77*4882a593Smuzhiyun #define CLKID_UART2 68 78*4882a593Smuzhiyun #define CLKID_SANA 69 79*4882a593Smuzhiyun #define CLKID_VPU_INTR 70 80*4882a593Smuzhiyun #define CLKID_SEC_AHB_AHB3_BRIDGE 71 81*4882a593Smuzhiyun #define CLKID_CLK81_A9 72 82*4882a593Smuzhiyun #define CLKID_VCLK2_VENCI0 73 83*4882a593Smuzhiyun #define CLKID_VCLK2_VENCI1 74 84*4882a593Smuzhiyun #define CLKID_VCLK2_VENCP0 75 85*4882a593Smuzhiyun #define CLKID_VCLK2_VENCP1 76 86*4882a593Smuzhiyun #define CLKID_GCLK_VENCI_INT 77 87*4882a593Smuzhiyun #define CLKID_GCLK_VENCP_INT 78 88*4882a593Smuzhiyun #define CLKID_DAC_CLK 79 89*4882a593Smuzhiyun #define CLKID_AOCLK_GATE 80 90*4882a593Smuzhiyun #define CLKID_IEC958_GATE 81 91*4882a593Smuzhiyun #define CLKID_ENC480P 82 92*4882a593Smuzhiyun #define CLKID_RNG1 83 93*4882a593Smuzhiyun #define CLKID_GCLK_VENCL_INT 84 94*4882a593Smuzhiyun #define CLKID_VCLK2_VENCLMCC 85 95*4882a593Smuzhiyun #define CLKID_VCLK2_VENCL 86 96*4882a593Smuzhiyun #define CLKID_VCLK2_OTHER 87 97*4882a593Smuzhiyun #define CLKID_EDP 88 98*4882a593Smuzhiyun #define CLKID_AO_MEDIA_CPU 89 99*4882a593Smuzhiyun #define CLKID_AO_AHB_SRAM 90 100*4882a593Smuzhiyun #define CLKID_AO_AHB_BUS 91 101*4882a593Smuzhiyun #define CLKID_AO_IFACE 92 102*4882a593Smuzhiyun #define CLKID_MPLL0 93 103*4882a593Smuzhiyun #define CLKID_MPLL1 94 104*4882a593Smuzhiyun #define CLKID_MPLL2 95 105*4882a593Smuzhiyun #define CLKID_NAND_CLK 112 106*4882a593Smuzhiyun #define CLKID_APB 124 107*4882a593Smuzhiyun #define CLKID_PERIPH 126 108*4882a593Smuzhiyun #define CLKID_AXI 128 109*4882a593Smuzhiyun #define CLKID_L2_DRAM 130 110*4882a593Smuzhiyun #define CLKID_HDMI_SYS 174 111*4882a593Smuzhiyun #define CLKID_VPU 190 112*4882a593Smuzhiyun #define CLKID_VDEC_1 196 113*4882a593Smuzhiyun #define CLKID_VDEC_HCODEC 199 114*4882a593Smuzhiyun #define CLKID_VDEC_2 202 115*4882a593Smuzhiyun #define CLKID_VDEC_HEVC 206 116*4882a593Smuzhiyun #define CLKID_CTS_AMCLK 209 117*4882a593Smuzhiyun #define CLKID_CTS_MCLK_I958 212 118*4882a593Smuzhiyun #define CLKID_CTS_I958 213 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #endif /* __MESON8B_CLKC_H */ 121