1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __DTS_MARVELL_PXA910_CLOCK_H 3*4882a593Smuzhiyun #define __DTS_MARVELL_PXA910_CLOCK_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* fixed clocks and plls */ 6*4882a593Smuzhiyun #define PXA910_CLK_CLK32 1 7*4882a593Smuzhiyun #define PXA910_CLK_VCTCXO 2 8*4882a593Smuzhiyun #define PXA910_CLK_PLL1 3 9*4882a593Smuzhiyun #define PXA910_CLK_PLL1_2 8 10*4882a593Smuzhiyun #define PXA910_CLK_PLL1_4 9 11*4882a593Smuzhiyun #define PXA910_CLK_PLL1_8 10 12*4882a593Smuzhiyun #define PXA910_CLK_PLL1_16 11 13*4882a593Smuzhiyun #define PXA910_CLK_PLL1_6 12 14*4882a593Smuzhiyun #define PXA910_CLK_PLL1_12 13 15*4882a593Smuzhiyun #define PXA910_CLK_PLL1_24 14 16*4882a593Smuzhiyun #define PXA910_CLK_PLL1_48 15 17*4882a593Smuzhiyun #define PXA910_CLK_PLL1_96 16 18*4882a593Smuzhiyun #define PXA910_CLK_PLL1_13 17 19*4882a593Smuzhiyun #define PXA910_CLK_PLL1_13_1_5 18 20*4882a593Smuzhiyun #define PXA910_CLK_PLL1_2_1_5 19 21*4882a593Smuzhiyun #define PXA910_CLK_PLL1_3_16 20 22*4882a593Smuzhiyun #define PXA910_CLK_PLL1_192 21 23*4882a593Smuzhiyun #define PXA910_CLK_UART_PLL 27 24*4882a593Smuzhiyun #define PXA910_CLK_USB_PLL 28 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* apb periphrals */ 27*4882a593Smuzhiyun #define PXA910_CLK_TWSI0 60 28*4882a593Smuzhiyun #define PXA910_CLK_TWSI1 61 29*4882a593Smuzhiyun #define PXA910_CLK_TWSI2 62 30*4882a593Smuzhiyun #define PXA910_CLK_TWSI3 63 31*4882a593Smuzhiyun #define PXA910_CLK_GPIO 64 32*4882a593Smuzhiyun #define PXA910_CLK_KPC 65 33*4882a593Smuzhiyun #define PXA910_CLK_RTC 66 34*4882a593Smuzhiyun #define PXA910_CLK_PWM0 67 35*4882a593Smuzhiyun #define PXA910_CLK_PWM1 68 36*4882a593Smuzhiyun #define PXA910_CLK_PWM2 69 37*4882a593Smuzhiyun #define PXA910_CLK_PWM3 70 38*4882a593Smuzhiyun #define PXA910_CLK_UART0 71 39*4882a593Smuzhiyun #define PXA910_CLK_UART1 72 40*4882a593Smuzhiyun #define PXA910_CLK_UART2 73 41*4882a593Smuzhiyun #define PXA910_CLK_SSP0 74 42*4882a593Smuzhiyun #define PXA910_CLK_SSP1 75 43*4882a593Smuzhiyun #define PXA910_CLK_TIMER0 76 44*4882a593Smuzhiyun #define PXA910_CLK_TIMER1 77 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* axi periphrals */ 47*4882a593Smuzhiyun #define PXA910_CLK_DFC 100 48*4882a593Smuzhiyun #define PXA910_CLK_SDH0 101 49*4882a593Smuzhiyun #define PXA910_CLK_SDH1 102 50*4882a593Smuzhiyun #define PXA910_CLK_SDH2 103 51*4882a593Smuzhiyun #define PXA910_CLK_USB 104 52*4882a593Smuzhiyun #define PXA910_CLK_SPH 105 53*4882a593Smuzhiyun #define PXA910_CLK_DISP0 106 54*4882a593Smuzhiyun #define PXA910_CLK_CCIC0 107 55*4882a593Smuzhiyun #define PXA910_CLK_CCIC0_PHY 108 56*4882a593Smuzhiyun #define PXA910_CLK_CCIC0_SPHY 109 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define PXA910_NR_CLKS 200 59*4882a593Smuzhiyun #endif 60