1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __DTS_MARVELL_PXA1928_CLOCK_H 3*4882a593Smuzhiyun #define __DTS_MARVELL_PXA1928_CLOCK_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * Clock ID values here correspond to the control register offset/4. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* apb peripherals */ 10*4882a593Smuzhiyun #define PXA1928_CLK_RTC 0x00 11*4882a593Smuzhiyun #define PXA1928_CLK_TWSI0 0x01 12*4882a593Smuzhiyun #define PXA1928_CLK_TWSI1 0x02 13*4882a593Smuzhiyun #define PXA1928_CLK_TWSI2 0x03 14*4882a593Smuzhiyun #define PXA1928_CLK_TWSI3 0x04 15*4882a593Smuzhiyun #define PXA1928_CLK_OWIRE 0x05 16*4882a593Smuzhiyun #define PXA1928_CLK_KPC 0x06 17*4882a593Smuzhiyun #define PXA1928_CLK_TB_ROTARY 0x07 18*4882a593Smuzhiyun #define PXA1928_CLK_SW_JTAG 0x08 19*4882a593Smuzhiyun #define PXA1928_CLK_TIMER1 0x09 20*4882a593Smuzhiyun #define PXA1928_CLK_UART0 0x0b 21*4882a593Smuzhiyun #define PXA1928_CLK_UART1 0x0c 22*4882a593Smuzhiyun #define PXA1928_CLK_UART2 0x0d 23*4882a593Smuzhiyun #define PXA1928_CLK_GPIO 0x0e 24*4882a593Smuzhiyun #define PXA1928_CLK_PWM0 0x0f 25*4882a593Smuzhiyun #define PXA1928_CLK_PWM1 0x10 26*4882a593Smuzhiyun #define PXA1928_CLK_PWM2 0x11 27*4882a593Smuzhiyun #define PXA1928_CLK_PWM3 0x12 28*4882a593Smuzhiyun #define PXA1928_CLK_SSP0 0x13 29*4882a593Smuzhiyun #define PXA1928_CLK_SSP1 0x14 30*4882a593Smuzhiyun #define PXA1928_CLK_SSP2 0x15 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define PXA1928_CLK_TWSI4 0x1f 33*4882a593Smuzhiyun #define PXA1928_CLK_TWSI5 0x20 34*4882a593Smuzhiyun #define PXA1928_CLK_UART3 0x22 35*4882a593Smuzhiyun #define PXA1928_CLK_THSENS_GLOB 0x24 36*4882a593Smuzhiyun #define PXA1928_CLK_THSENS_CPU 0x26 37*4882a593Smuzhiyun #define PXA1928_CLK_THSENS_VPU 0x27 38*4882a593Smuzhiyun #define PXA1928_CLK_THSENS_GC 0x28 39*4882a593Smuzhiyun #define PXA1928_APBC_NR_CLKS 0x30 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* axi peripherals */ 43*4882a593Smuzhiyun #define PXA1928_CLK_SDH0 0x15 44*4882a593Smuzhiyun #define PXA1928_CLK_SDH1 0x16 45*4882a593Smuzhiyun #define PXA1928_CLK_USB 0x17 46*4882a593Smuzhiyun #define PXA1928_CLK_NAND 0x18 47*4882a593Smuzhiyun #define PXA1928_CLK_DMA 0x19 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define PXA1928_CLK_SDH2 0x3a 50*4882a593Smuzhiyun #define PXA1928_CLK_SDH3 0x3b 51*4882a593Smuzhiyun #define PXA1928_CLK_HSIC 0x3e 52*4882a593Smuzhiyun #define PXA1928_CLK_SDH4 0x57 53*4882a593Smuzhiyun #define PXA1928_CLK_GC3D 0x5d 54*4882a593Smuzhiyun #define PXA1928_CLK_GC2D 0x5f 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define PXA1928_APMU_NR_CLKS 0x60 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #endif 59