1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __DTS_MARVELL_MMP2_CLOCK_H 3*4882a593Smuzhiyun #define __DTS_MARVELL_MMP2_CLOCK_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* fixed clocks and plls */ 6*4882a593Smuzhiyun #define MMP2_CLK_CLK32 1 7*4882a593Smuzhiyun #define MMP2_CLK_VCTCXO 2 8*4882a593Smuzhiyun #define MMP2_CLK_PLL1 3 9*4882a593Smuzhiyun #define MMP2_CLK_PLL1_2 8 10*4882a593Smuzhiyun #define MMP2_CLK_PLL1_4 9 11*4882a593Smuzhiyun #define MMP2_CLK_PLL1_8 10 12*4882a593Smuzhiyun #define MMP2_CLK_PLL1_16 11 13*4882a593Smuzhiyun #define MMP2_CLK_PLL1_3 12 14*4882a593Smuzhiyun #define MMP2_CLK_PLL1_6 13 15*4882a593Smuzhiyun #define MMP2_CLK_PLL1_12 14 16*4882a593Smuzhiyun #define MMP2_CLK_PLL1_20 15 17*4882a593Smuzhiyun #define MMP2_CLK_PLL2 16 18*4882a593Smuzhiyun #define MMP2_CLK_PLL2_2 17 19*4882a593Smuzhiyun #define MMP2_CLK_PLL2_4 18 20*4882a593Smuzhiyun #define MMP2_CLK_PLL2_8 19 21*4882a593Smuzhiyun #define MMP2_CLK_PLL2_16 20 22*4882a593Smuzhiyun #define MMP2_CLK_PLL2_3 21 23*4882a593Smuzhiyun #define MMP2_CLK_PLL2_6 22 24*4882a593Smuzhiyun #define MMP2_CLK_PLL2_12 23 25*4882a593Smuzhiyun #define MMP2_CLK_VCTCXO_2 24 26*4882a593Smuzhiyun #define MMP2_CLK_VCTCXO_4 25 27*4882a593Smuzhiyun #define MMP2_CLK_UART_PLL 26 28*4882a593Smuzhiyun #define MMP2_CLK_USB_PLL 27 29*4882a593Smuzhiyun #define MMP3_CLK_PLL1_P 28 30*4882a593Smuzhiyun #define MMP3_CLK_PLL2_P 29 31*4882a593Smuzhiyun #define MMP3_CLK_PLL3 30 32*4882a593Smuzhiyun #define MMP2_CLK_I2S0 31 33*4882a593Smuzhiyun #define MMP2_CLK_I2S1 32 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* apb periphrals */ 36*4882a593Smuzhiyun #define MMP2_CLK_TWSI0 60 37*4882a593Smuzhiyun #define MMP2_CLK_TWSI1 61 38*4882a593Smuzhiyun #define MMP2_CLK_TWSI2 62 39*4882a593Smuzhiyun #define MMP2_CLK_TWSI3 63 40*4882a593Smuzhiyun #define MMP2_CLK_TWSI4 64 41*4882a593Smuzhiyun #define MMP2_CLK_TWSI5 65 42*4882a593Smuzhiyun #define MMP2_CLK_GPIO 66 43*4882a593Smuzhiyun #define MMP2_CLK_KPC 67 44*4882a593Smuzhiyun #define MMP2_CLK_RTC 68 45*4882a593Smuzhiyun #define MMP2_CLK_PWM0 69 46*4882a593Smuzhiyun #define MMP2_CLK_PWM1 70 47*4882a593Smuzhiyun #define MMP2_CLK_PWM2 71 48*4882a593Smuzhiyun #define MMP2_CLK_PWM3 72 49*4882a593Smuzhiyun #define MMP2_CLK_UART0 73 50*4882a593Smuzhiyun #define MMP2_CLK_UART1 74 51*4882a593Smuzhiyun #define MMP2_CLK_UART2 75 52*4882a593Smuzhiyun #define MMP2_CLK_UART3 76 53*4882a593Smuzhiyun #define MMP2_CLK_SSP0 77 54*4882a593Smuzhiyun #define MMP2_CLK_SSP1 78 55*4882a593Smuzhiyun #define MMP2_CLK_SSP2 79 56*4882a593Smuzhiyun #define MMP2_CLK_SSP3 80 57*4882a593Smuzhiyun #define MMP2_CLK_TIMER 81 58*4882a593Smuzhiyun #define MMP2_CLK_THERMAL0 82 59*4882a593Smuzhiyun #define MMP3_CLK_THERMAL1 83 60*4882a593Smuzhiyun #define MMP3_CLK_THERMAL2 84 61*4882a593Smuzhiyun #define MMP3_CLK_THERMAL3 85 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* axi periphrals */ 64*4882a593Smuzhiyun #define MMP2_CLK_SDH0 101 65*4882a593Smuzhiyun #define MMP2_CLK_SDH1 102 66*4882a593Smuzhiyun #define MMP2_CLK_SDH2 103 67*4882a593Smuzhiyun #define MMP2_CLK_SDH3 104 68*4882a593Smuzhiyun #define MMP2_CLK_USB 105 69*4882a593Smuzhiyun #define MMP2_CLK_DISP0 106 70*4882a593Smuzhiyun #define MMP2_CLK_DISP0_MUX 107 71*4882a593Smuzhiyun #define MMP2_CLK_DISP0_SPHY 108 72*4882a593Smuzhiyun #define MMP2_CLK_DISP1 109 73*4882a593Smuzhiyun #define MMP2_CLK_DISP1_MUX 110 74*4882a593Smuzhiyun #define MMP2_CLK_CCIC_ARBITER 111 75*4882a593Smuzhiyun #define MMP2_CLK_CCIC0 112 76*4882a593Smuzhiyun #define MMP2_CLK_CCIC0_MIX 113 77*4882a593Smuzhiyun #define MMP2_CLK_CCIC0_PHY 114 78*4882a593Smuzhiyun #define MMP2_CLK_CCIC0_SPHY 115 79*4882a593Smuzhiyun #define MMP2_CLK_CCIC1 116 80*4882a593Smuzhiyun #define MMP2_CLK_CCIC1_MIX 117 81*4882a593Smuzhiyun #define MMP2_CLK_CCIC1_PHY 118 82*4882a593Smuzhiyun #define MMP2_CLK_CCIC1_SPHY 119 83*4882a593Smuzhiyun #define MMP2_CLK_DISP0_LCDC 120 84*4882a593Smuzhiyun #define MMP2_CLK_USBHSIC0 121 85*4882a593Smuzhiyun #define MMP2_CLK_USBHSIC1 122 86*4882a593Smuzhiyun #define MMP2_CLK_GPU_BUS 123 87*4882a593Smuzhiyun #define MMP3_CLK_GPU_BUS MMP2_CLK_GPU_BUS 88*4882a593Smuzhiyun #define MMP2_CLK_GPU_3D 124 89*4882a593Smuzhiyun #define MMP3_CLK_GPU_3D MMP2_CLK_GPU_3D 90*4882a593Smuzhiyun #define MMP3_CLK_GPU_2D 125 91*4882a593Smuzhiyun #define MMP3_CLK_SDH4 126 92*4882a593Smuzhiyun #define MMP2_CLK_AUDIO 127 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define MMP2_NR_CLKS 200 95*4882a593Smuzhiyun #endif 96