1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2014 LSI Corporation 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _DT_BINDINGS_CLK_AXM5516_H 7*4882a593Smuzhiyun #define _DT_BINDINGS_CLK_AXM5516_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define AXXIA_CLK_FAB_PLL 0 10*4882a593Smuzhiyun #define AXXIA_CLK_CPU_PLL 1 11*4882a593Smuzhiyun #define AXXIA_CLK_SYS_PLL 2 12*4882a593Smuzhiyun #define AXXIA_CLK_SM0_PLL 3 13*4882a593Smuzhiyun #define AXXIA_CLK_SM1_PLL 4 14*4882a593Smuzhiyun #define AXXIA_CLK_FAB_DIV 5 15*4882a593Smuzhiyun #define AXXIA_CLK_SYS_DIV 6 16*4882a593Smuzhiyun #define AXXIA_CLK_NRCP_DIV 7 17*4882a593Smuzhiyun #define AXXIA_CLK_CPU0_DIV 8 18*4882a593Smuzhiyun #define AXXIA_CLK_CPU1_DIV 9 19*4882a593Smuzhiyun #define AXXIA_CLK_CPU2_DIV 10 20*4882a593Smuzhiyun #define AXXIA_CLK_CPU3_DIV 11 21*4882a593Smuzhiyun #define AXXIA_CLK_PER_DIV 12 22*4882a593Smuzhiyun #define AXXIA_CLK_MMC_DIV 13 23*4882a593Smuzhiyun #define AXXIA_CLK_FAB 14 24*4882a593Smuzhiyun #define AXXIA_CLK_SYS 15 25*4882a593Smuzhiyun #define AXXIA_CLK_NRCP 16 26*4882a593Smuzhiyun #define AXXIA_CLK_CPU0 17 27*4882a593Smuzhiyun #define AXXIA_CLK_CPU1 18 28*4882a593Smuzhiyun #define AXXIA_CLK_CPU2 19 29*4882a593Smuzhiyun #define AXXIA_CLK_CPU3 20 30*4882a593Smuzhiyun #define AXXIA_CLK_PER 21 31*4882a593Smuzhiyun #define AXXIA_CLK_MMC 22 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #endif 34