1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2015 Vladimir Zapolskiy <vz@mleia.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This code is released using a dual license strategy: BSD/GPL 5*4882a593Smuzhiyun * You can choose the licence that better fits your requirements. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Released under the terms of 3-clause BSD License 8*4882a593Smuzhiyun * Released under the terms of GNU General Public License Version 2.0 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __DT_BINDINGS_LPC32XX_CLOCK_H 13*4882a593Smuzhiyun #define __DT_BINDINGS_LPC32XX_CLOCK_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* LPC32XX System Control Block clocks */ 16*4882a593Smuzhiyun #define LPC32XX_CLK_RTC 1 17*4882a593Smuzhiyun #define LPC32XX_CLK_DMA 2 18*4882a593Smuzhiyun #define LPC32XX_CLK_MLC 3 19*4882a593Smuzhiyun #define LPC32XX_CLK_SLC 4 20*4882a593Smuzhiyun #define LPC32XX_CLK_LCD 5 21*4882a593Smuzhiyun #define LPC32XX_CLK_MAC 6 22*4882a593Smuzhiyun #define LPC32XX_CLK_SD 7 23*4882a593Smuzhiyun #define LPC32XX_CLK_DDRAM 8 24*4882a593Smuzhiyun #define LPC32XX_CLK_SSP0 9 25*4882a593Smuzhiyun #define LPC32XX_CLK_SSP1 10 26*4882a593Smuzhiyun #define LPC32XX_CLK_UART3 11 27*4882a593Smuzhiyun #define LPC32XX_CLK_UART4 12 28*4882a593Smuzhiyun #define LPC32XX_CLK_UART5 13 29*4882a593Smuzhiyun #define LPC32XX_CLK_UART6 14 30*4882a593Smuzhiyun #define LPC32XX_CLK_IRDA 15 31*4882a593Smuzhiyun #define LPC32XX_CLK_I2C1 16 32*4882a593Smuzhiyun #define LPC32XX_CLK_I2C2 17 33*4882a593Smuzhiyun #define LPC32XX_CLK_TIMER0 18 34*4882a593Smuzhiyun #define LPC32XX_CLK_TIMER1 19 35*4882a593Smuzhiyun #define LPC32XX_CLK_TIMER2 20 36*4882a593Smuzhiyun #define LPC32XX_CLK_TIMER3 21 37*4882a593Smuzhiyun #define LPC32XX_CLK_TIMER4 22 38*4882a593Smuzhiyun #define LPC32XX_CLK_TIMER5 23 39*4882a593Smuzhiyun #define LPC32XX_CLK_WDOG 24 40*4882a593Smuzhiyun #define LPC32XX_CLK_I2S0 25 41*4882a593Smuzhiyun #define LPC32XX_CLK_I2S1 26 42*4882a593Smuzhiyun #define LPC32XX_CLK_SPI1 27 43*4882a593Smuzhiyun #define LPC32XX_CLK_SPI2 28 44*4882a593Smuzhiyun #define LPC32XX_CLK_MCPWM 29 45*4882a593Smuzhiyun #define LPC32XX_CLK_HSTIMER 30 46*4882a593Smuzhiyun #define LPC32XX_CLK_KEY 31 47*4882a593Smuzhiyun #define LPC32XX_CLK_PWM1 32 48*4882a593Smuzhiyun #define LPC32XX_CLK_PWM2 33 49*4882a593Smuzhiyun #define LPC32XX_CLK_ADC 34 50*4882a593Smuzhiyun #define LPC32XX_CLK_HCLK_PLL 35 51*4882a593Smuzhiyun #define LPC32XX_CLK_PERIPH 36 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* LPC32XX USB clocks */ 54*4882a593Smuzhiyun #define LPC32XX_USB_CLK_I2C 1 55*4882a593Smuzhiyun #define LPC32XX_USB_CLK_DEVICE 2 56*4882a593Smuzhiyun #define LPC32XX_USB_CLK_HOST 3 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #endif /* __DT_BINDINGS_LPC32XX_CLOCK_H */ 59