1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This code is released using a dual license strategy: BSD/GPL 5*4882a593Smuzhiyun * You can choose the licence that better fits your requirements. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Released under the terms of 3-clause BSD License 8*4882a593Smuzhiyun * Released under the terms of GNU General Public License Version 2.0 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* LPC18xx/43xx base clock ids */ 13*4882a593Smuzhiyun #define BASE_SAFE_CLK 0 14*4882a593Smuzhiyun #define BASE_USB0_CLK 1 15*4882a593Smuzhiyun #define BASE_PERIPH_CLK 2 16*4882a593Smuzhiyun #define BASE_USB1_CLK 3 17*4882a593Smuzhiyun #define BASE_CPU_CLK 4 18*4882a593Smuzhiyun #define BASE_SPIFI_CLK 5 19*4882a593Smuzhiyun #define BASE_SPI_CLK 6 20*4882a593Smuzhiyun #define BASE_PHY_RX_CLK 7 21*4882a593Smuzhiyun #define BASE_PHY_TX_CLK 8 22*4882a593Smuzhiyun #define BASE_APB1_CLK 9 23*4882a593Smuzhiyun #define BASE_APB3_CLK 10 24*4882a593Smuzhiyun #define BASE_LCD_CLK 11 25*4882a593Smuzhiyun #define BASE_ADCHS_CLK 12 26*4882a593Smuzhiyun #define BASE_SDIO_CLK 13 27*4882a593Smuzhiyun #define BASE_SSP0_CLK 14 28*4882a593Smuzhiyun #define BASE_SSP1_CLK 15 29*4882a593Smuzhiyun #define BASE_UART0_CLK 16 30*4882a593Smuzhiyun #define BASE_UART1_CLK 17 31*4882a593Smuzhiyun #define BASE_UART2_CLK 18 32*4882a593Smuzhiyun #define BASE_UART3_CLK 19 33*4882a593Smuzhiyun #define BASE_OUT_CLK 20 34*4882a593Smuzhiyun #define BASE_RES1_CLK 21 35*4882a593Smuzhiyun #define BASE_RES2_CLK 22 36*4882a593Smuzhiyun #define BASE_RES3_CLK 23 37*4882a593Smuzhiyun #define BASE_RES4_CLK 24 38*4882a593Smuzhiyun #define BASE_AUDIO_CLK 25 39*4882a593Smuzhiyun #define BASE_CGU_OUT0_CLK 26 40*4882a593Smuzhiyun #define BASE_CGU_OUT1_CLK 27 41*4882a593Smuzhiyun #define BASE_CLK_MAX (BASE_CGU_OUT1_CLK + 1) 42