1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> 4*4882a593Smuzhiyun * Copyright (c) 2020 Western Digital Corporation or its affiliates. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef K210_CLK_H 7*4882a593Smuzhiyun #define K210_CLK_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* 10*4882a593Smuzhiyun * Arbitrary identifiers for clocks. 11*4882a593Smuzhiyun * The structure is: in0 -> pll0 -> aclk -> cpu 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * Since we use the hardware defaults for now, set all these to the same clock. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define K210_CLK_PLL0 0 16*4882a593Smuzhiyun #define K210_CLK_PLL1 0 17*4882a593Smuzhiyun #define K210_CLK_ACLK 0 18*4882a593Smuzhiyun #define K210_CLK_CPU 0 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #endif /* K210_CLK_H */ 21