1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides clock numbers for the ingenic,jz4780-cgu DT binding. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * They are roughly ordered as: 6*4882a593Smuzhiyun * - external clocks 7*4882a593Smuzhiyun * - PLLs 8*4882a593Smuzhiyun * - muxes/dividers in the order they appear in the jz4780 programmers manual 9*4882a593Smuzhiyun * - gates in order of their bit in the CLKGR* registers 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ 13*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define JZ4780_CLK_EXCLK 0 16*4882a593Smuzhiyun #define JZ4780_CLK_RTCLK 1 17*4882a593Smuzhiyun #define JZ4780_CLK_APLL 2 18*4882a593Smuzhiyun #define JZ4780_CLK_MPLL 3 19*4882a593Smuzhiyun #define JZ4780_CLK_EPLL 4 20*4882a593Smuzhiyun #define JZ4780_CLK_VPLL 5 21*4882a593Smuzhiyun #define JZ4780_CLK_OTGPHY 6 22*4882a593Smuzhiyun #define JZ4780_CLK_SCLKA 7 23*4882a593Smuzhiyun #define JZ4780_CLK_CPUMUX 8 24*4882a593Smuzhiyun #define JZ4780_CLK_CPU 9 25*4882a593Smuzhiyun #define JZ4780_CLK_L2CACHE 10 26*4882a593Smuzhiyun #define JZ4780_CLK_AHB0 11 27*4882a593Smuzhiyun #define JZ4780_CLK_AHB2PMUX 12 28*4882a593Smuzhiyun #define JZ4780_CLK_AHB2 13 29*4882a593Smuzhiyun #define JZ4780_CLK_PCLK 14 30*4882a593Smuzhiyun #define JZ4780_CLK_DDR 15 31*4882a593Smuzhiyun #define JZ4780_CLK_VPU 16 32*4882a593Smuzhiyun #define JZ4780_CLK_I2SPLL 17 33*4882a593Smuzhiyun #define JZ4780_CLK_I2S 18 34*4882a593Smuzhiyun #define JZ4780_CLK_LCD0PIXCLK 19 35*4882a593Smuzhiyun #define JZ4780_CLK_LCD1PIXCLK 20 36*4882a593Smuzhiyun #define JZ4780_CLK_MSCMUX 21 37*4882a593Smuzhiyun #define JZ4780_CLK_MSC0 22 38*4882a593Smuzhiyun #define JZ4780_CLK_MSC1 23 39*4882a593Smuzhiyun #define JZ4780_CLK_MSC2 24 40*4882a593Smuzhiyun #define JZ4780_CLK_UHC 25 41*4882a593Smuzhiyun #define JZ4780_CLK_SSIPLL 26 42*4882a593Smuzhiyun #define JZ4780_CLK_SSI 27 43*4882a593Smuzhiyun #define JZ4780_CLK_CIMMCLK 28 44*4882a593Smuzhiyun #define JZ4780_CLK_PCMPLL 29 45*4882a593Smuzhiyun #define JZ4780_CLK_PCM 30 46*4882a593Smuzhiyun #define JZ4780_CLK_GPU 31 47*4882a593Smuzhiyun #define JZ4780_CLK_HDMI 32 48*4882a593Smuzhiyun #define JZ4780_CLK_BCH 33 49*4882a593Smuzhiyun #define JZ4780_CLK_NEMC 34 50*4882a593Smuzhiyun #define JZ4780_CLK_OTG0 35 51*4882a593Smuzhiyun #define JZ4780_CLK_SSI0 36 52*4882a593Smuzhiyun #define JZ4780_CLK_SMB0 37 53*4882a593Smuzhiyun #define JZ4780_CLK_SMB1 38 54*4882a593Smuzhiyun #define JZ4780_CLK_SCC 39 55*4882a593Smuzhiyun #define JZ4780_CLK_AIC 40 56*4882a593Smuzhiyun #define JZ4780_CLK_TSSI0 41 57*4882a593Smuzhiyun #define JZ4780_CLK_OWI 42 58*4882a593Smuzhiyun #define JZ4780_CLK_KBC 43 59*4882a593Smuzhiyun #define JZ4780_CLK_SADC 44 60*4882a593Smuzhiyun #define JZ4780_CLK_UART0 45 61*4882a593Smuzhiyun #define JZ4780_CLK_UART1 46 62*4882a593Smuzhiyun #define JZ4780_CLK_UART2 47 63*4882a593Smuzhiyun #define JZ4780_CLK_UART3 48 64*4882a593Smuzhiyun #define JZ4780_CLK_SSI1 49 65*4882a593Smuzhiyun #define JZ4780_CLK_SSI2 50 66*4882a593Smuzhiyun #define JZ4780_CLK_PDMA 51 67*4882a593Smuzhiyun #define JZ4780_CLK_GPS 52 68*4882a593Smuzhiyun #define JZ4780_CLK_MAC 53 69*4882a593Smuzhiyun #define JZ4780_CLK_SMB2 54 70*4882a593Smuzhiyun #define JZ4780_CLK_CIM 55 71*4882a593Smuzhiyun #define JZ4780_CLK_LCD 56 72*4882a593Smuzhiyun #define JZ4780_CLK_TVE 57 73*4882a593Smuzhiyun #define JZ4780_CLK_IPU 58 74*4882a593Smuzhiyun #define JZ4780_CLK_DDR0 59 75*4882a593Smuzhiyun #define JZ4780_CLK_DDR1 60 76*4882a593Smuzhiyun #define JZ4780_CLK_SMB3 61 77*4882a593Smuzhiyun #define JZ4780_CLK_TSSI1 62 78*4882a593Smuzhiyun #define JZ4780_CLK_COMPRESS 63 79*4882a593Smuzhiyun #define JZ4780_CLK_AIC1 64 80*4882a593Smuzhiyun #define JZ4780_CLK_GPVLC 65 81*4882a593Smuzhiyun #define JZ4780_CLK_OTG1 66 82*4882a593Smuzhiyun #define JZ4780_CLK_UART4 67 83*4882a593Smuzhiyun #define JZ4780_CLK_AHBMON 68 84*4882a593Smuzhiyun #define JZ4780_CLK_SMB4 69 85*4882a593Smuzhiyun #define JZ4780_CLK_DES 70 86*4882a593Smuzhiyun #define JZ4780_CLK_X2D 71 87*4882a593Smuzhiyun #define JZ4780_CLK_CORE1 72 88*4882a593Smuzhiyun #define JZ4780_CLK_EXCLK_DIV512 73 89*4882a593Smuzhiyun #define JZ4780_CLK_RTC 74 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */ 92