1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This header provides clock numbers for the ingenic,jz4770-cgu DT binding. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ 7*4882a593Smuzhiyun #define __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define JZ4770_CLK_EXT 0 10*4882a593Smuzhiyun #define JZ4770_CLK_OSC32K 1 11*4882a593Smuzhiyun #define JZ4770_CLK_PLL0 2 12*4882a593Smuzhiyun #define JZ4770_CLK_PLL1 3 13*4882a593Smuzhiyun #define JZ4770_CLK_CCLK 4 14*4882a593Smuzhiyun #define JZ4770_CLK_H0CLK 5 15*4882a593Smuzhiyun #define JZ4770_CLK_H1CLK 6 16*4882a593Smuzhiyun #define JZ4770_CLK_H2CLK 7 17*4882a593Smuzhiyun #define JZ4770_CLK_C1CLK 8 18*4882a593Smuzhiyun #define JZ4770_CLK_PCLK 9 19*4882a593Smuzhiyun #define JZ4770_CLK_MMC0_MUX 10 20*4882a593Smuzhiyun #define JZ4770_CLK_MMC0 11 21*4882a593Smuzhiyun #define JZ4770_CLK_MMC1_MUX 12 22*4882a593Smuzhiyun #define JZ4770_CLK_MMC1 13 23*4882a593Smuzhiyun #define JZ4770_CLK_MMC2_MUX 14 24*4882a593Smuzhiyun #define JZ4770_CLK_MMC2 15 25*4882a593Smuzhiyun #define JZ4770_CLK_CIM 16 26*4882a593Smuzhiyun #define JZ4770_CLK_UHC 17 27*4882a593Smuzhiyun #define JZ4770_CLK_GPU 18 28*4882a593Smuzhiyun #define JZ4770_CLK_BCH 19 29*4882a593Smuzhiyun #define JZ4770_CLK_LPCLK_MUX 20 30*4882a593Smuzhiyun #define JZ4770_CLK_GPS 21 31*4882a593Smuzhiyun #define JZ4770_CLK_SSI_MUX 22 32*4882a593Smuzhiyun #define JZ4770_CLK_PCM_MUX 23 33*4882a593Smuzhiyun #define JZ4770_CLK_I2S 24 34*4882a593Smuzhiyun #define JZ4770_CLK_OTG 25 35*4882a593Smuzhiyun #define JZ4770_CLK_SSI0 26 36*4882a593Smuzhiyun #define JZ4770_CLK_SSI1 27 37*4882a593Smuzhiyun #define JZ4770_CLK_SSI2 28 38*4882a593Smuzhiyun #define JZ4770_CLK_PCM0 29 39*4882a593Smuzhiyun #define JZ4770_CLK_PCM1 30 40*4882a593Smuzhiyun #define JZ4770_CLK_DMA 31 41*4882a593Smuzhiyun #define JZ4770_CLK_I2C0 32 42*4882a593Smuzhiyun #define JZ4770_CLK_I2C1 33 43*4882a593Smuzhiyun #define JZ4770_CLK_I2C2 34 44*4882a593Smuzhiyun #define JZ4770_CLK_UART0 35 45*4882a593Smuzhiyun #define JZ4770_CLK_UART1 36 46*4882a593Smuzhiyun #define JZ4770_CLK_UART2 37 47*4882a593Smuzhiyun #define JZ4770_CLK_UART3 38 48*4882a593Smuzhiyun #define JZ4770_CLK_IPU 39 49*4882a593Smuzhiyun #define JZ4770_CLK_ADC 40 50*4882a593Smuzhiyun #define JZ4770_CLK_AIC 41 51*4882a593Smuzhiyun #define JZ4770_CLK_AUX 42 52*4882a593Smuzhiyun #define JZ4770_CLK_VPU 43 53*4882a593Smuzhiyun #define JZ4770_CLK_UHC_PHY 44 54*4882a593Smuzhiyun #define JZ4770_CLK_OTG_PHY 45 55*4882a593Smuzhiyun #define JZ4770_CLK_EXT512 46 56*4882a593Smuzhiyun #define JZ4770_CLK_RTC 47 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #endif /* __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ */ 59